An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists

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An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists (1999)

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by AJ Elbirt , W Yip , B Chetwynd , C Paar

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65 - 4 self

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@MISC{Elbirt99anfpga,
    author = {AJ Elbirt and W Yip and B Chetwynd and C Paar},
    title = {An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists},
    year = {1999}
}

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Abstract

The technical analysis used in determining which of the Advanced Encryption Standard candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrmmable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of FPGA implementations of four of the Advanced Encryption Standard candidate algorithm finalists. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high throughput implementations, which are required to support security for current and future high bandwidth applications.

Keyphrases

fpga implementation performance evaluation cryptographic algorithm agility physical security advanced encryption standard candidate software solution efficiency testing strong focus high throughput implementation technical analysis future high bandwidth application multiple architectural implementation option field programmable gate array attractive option software implementation hardware implementation advanced encryption algorithm encryption algorithm reprogrmmable device candidate algorithm

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