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@MISC{_,
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Abstract
This thesis focuses on the optimization methods for standard cell layouts. Standard cells are the most fundamental components of VLSI, and provide the building blocks for creating large complex functions in both application-specific and semi-custom domains. Therefore, their performance has significant effects on the final performance of the synthesized VLSI. We propose a minimum-width transistor placement and an intra-cell routing via Boolean satisfiability to optimize the area of the cell layouts. We also propose a comprehensive cell layout synthesis method and a cell layout de-compaction method for yield optimization. Chapter 2 proposes a minimum-width layout synthesis method for dual CMOS cells via Boolean Satisfiability (SAT). Cell layout synthesis problems, i.e., the transistor placement and the intra-cell routing problems are first transformed into SAT problems by this formulation. The proposed method guarantees to generate minimum-width cell layouts with routability under our layout styles. This method places complementary P and N type transistors individually during transistor placement, and can generate smaller width layout compared with the case of pairing the complementary P and N type transistors. The experimental results
Keyphrases
boolean satisfiability transistor placement type transistor sat problem synthesized vlsi minimum-width cell layout final performance intra-cell routing building block significant effect method guarantee minimum-width layout synthesis method comprehensive cell dual cmos cell semi-custom domain standard cell layout standard cell synthesis problem de-compaction method fundamental component optimization method width layout synthesis method intra-cell routing problem layout style yield optimization minimum-width transistor placement experimental result large complex function
