Route Packets, Not Wires: On-Chip Interconnection Networks

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Route Packets, Not Wires: On-Chip Interconnection Networks (2001)

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by William J. Dally , Brian Towles

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885 - 10 self

BibTeX

@MISC{Dally01routepackets,,
    author = {William J. Dally and Brian Towles},
    title = {Route Packets, Not Wires: On-Chip Interconnection Networks},
    year = {2001}
}

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Abstract

Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks. 1

Keyphrases

on-chip interconnection network route packet on-chip network structured network well-controlled electrical parameter area overhead top level wire ad-hoc global wiring system module facilitates modular design simple network timing iteration high-performance circuit

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