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Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators
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| Venue: | Proc. Int’l Conf. Hardware/Software Codesign and System Synthesis (CODES/ISSS 07), ACM Press, 2007 |
| Citations: | 6 - 1 self |
BibTeX
@INPROCEEDINGS{Stitt_threadwarping:,
author = {Greg Stitt and Frank Vahid},
title = {Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators},
booktitle = {Proc. Int’l Conf. Hardware/Software Codesign and System Synthesis (CODES/ISSS 07), ACM Press, 2007},
year = {},
pages = {93--98}
}
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Abstract
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and by allowing more threads to execute concurrently. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and FPGA—an advantage not shared by static compilation/synthesis approaches. We introduce a framework of architecture, CAD tools, and operating system that together support thread warping. We summarize experiments on an extensive architectural simulation framework we developed, showing application speedups of 4x to 502x, averaging 130x compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11x speedup.
Keyphrases
thread warping dynamic synthesis multiprocessor system thread accelerator single processor improves performance custom accelerator circuit important separation static compilation synthesis approach benchmark application application speedup dynamic optimization technique 64-processor system single-processor single-thread system warp processing extensive architectural simulation framework individual thread cad tool field-programmable gate array arm11 microprocessor different quantity
