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Modular minimization of deterministic finite-state machines (2001)
| Venue: | In 6th International Workshop on Formal Methods for Industrial Critical Systems |
| Citations: | 5 - 1 self |
BibTeX
@INPROCEEDINGS{Bustan01modularminimization,
author = {Doron Bustan},
title = {Modular minimization of deterministic finite-state machines},
booktitle = {In 6th International Workshop on Formal Methods for Industrial Critical Systems},
year = {2001},
pages = {163--178}
}
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Abstract
Abstract This work presents a modular technique for minimizing a deterministic finite-state machine (FSM) while preserving its equivalence to the original system. Being modular, the minimization technique should consume less time and space. Preserving equivalence, the resulting minimized model can be employed in both temporal logic model checking and sequential equivalence checking, thus reducing their time and space consumption. As deterministic FSMs are commonly used for modeling hardware designs, our approach is suitable for formal verification of such designs. We develop a new BDD framework for the representation and manipulation of functions and show how our minimization technique can be effectively implemented within this framework. 1 Introduction Due to the fast development of the hardware and software industry, there is a growing need for formal verification tools and techniques. Two widely used formal verification methods are temporal logic model checking and sequential equivalence checking. Temporal logic model checking is a method for verifying finite-state systems with respect to propositional temporal logic specifications. In sequential equivalence checking, two sequential hardware designs are compared for language equivalence, meaning that for every sequence of inputs, the two designs produce the same sequence of outputs. Both model checking and equivalence checking are fully automatic. However, they both suffer from the state explosion problem, that is to say, their space requirements are high and limit their applicability to large systems. Many approaches for overcoming the state explosion problem have been suggested, including abstraction, partial order reduction, modular verification methods, and symmetry [5]. All are aimed at reducing the size of the model to which formal verification methods are applied, thus extending their applicability to larger systems. When reduction methods are applied, the verification technique has to be able to deduce properties of the system by verifying the reduced model. We therefore require the result of the reduction to be equivalent to the original model.
Keyphrases
deterministic finite-state machine sequential equivalence checking temporal logic model checking modular minimization formal verification method minimization technique state explosion problem verification technique reduced model model checking equivalence checking hardware design reduction method minimized model modular verification method fast development formal verification language equivalence formal verification tool software industry propositional temporal logic specification modular technique original model deterministic fsms space consumption many approach partial order reduction introduction due finite-state system large system original system space requirement new bdd framework sequential hardware design
