DMCA
Efficient Weighted Pattern Generation Technique With Low Hardware Overhead
BibTeX
@MISC{Madhavi_efficientweighted,
author = {K. Veena Madhavi and Mrs M. Nirmala},
title = {Efficient Weighted Pattern Generation Technique With Low Hardware Overhead},
year = {}
}
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Abstract
Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this paper an accumulator-based 3-weight test pattern generation scheme is presented; the proposed scheme generates set of patterns with weights 0, 0.5, and 1. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. Comparisons with previously presented schemes indicate that the proposed scheme compares favorably with respect to the required hardware. Index Terms: BIST, test per clock, VLSI testing, weighted test pattern generation 1.
