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Static Routing in Symmetric Real-Time Network-on-Chips
| Citations: | 5 - 2 self |
BibTeX
@MISC{Brandner_staticrouting,
author = {Florian Brandner and Martin Schoeberl},
title = {Static Routing in Symmetric Real-Time Network-on-Chips},
year = {}
}
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Abstract
With the rising number of cores on a single chip the question on how to organize the communication among those cores becomes more and more relevant. A common solution is to use a network-on-chip (NoC) that provides communication bandwidth, routing, and arbitration among the cores. The use of NoCs in real-time systems is problematic, since the shared network and all cores connected to it have to be analyzed to derive time bounds of real-time tasks. We propose to use a statically scheduled, time-divisionmultiplexed NoC design that allows a decoupled analysis of individual real-time tasks. Our network provides virtual circuits between all cores. These virtual circuits are implemented by delivering messages periodically on a static, fixed routing schedule. Since the routing does not change, it can be pre-computed offline. This work focuses on the computation of routing schedules for symmetric NoC topologies, e.g., torus and hypercube. Due to the symmetry, the all-to-all communication can be modeled via simplified communication patterns that are concurrently processed by all routers. The scheduling problem is solved by a heuristic that tries to maximize the overlap of active patterns. Our experiments show that, for larger networks, our heuristic yields schedule lengths that are only 15 % to 20 % longer than theoretical lower bounds. Categories and Subject Descriptors C.3 [Special-Purpose and Application-Based Systems]: Real-time and embedded systems;
Keyphrases
static routing symmetric real-time network-on-chips virtual circuit application-based system communication bandwidth subject descriptor common solution pre-computed offline real-time task derive time bound communication pattern heuristic yield schedule length time-divisionmultiplexed noc design symmetric noc topology active pattern single chip individual real-time task real-time system scheduling problem all-to-all communication decoupled analysis embedded system
