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Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores
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BibTeX
@MISC{Udipi_rethinkingdram,
author = {Aniruddha N. Udipi and Rajeev Balasubramonian and Naveen Muralimanohar and Al Davis and Niladrish Chatterjee},
title = {Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores},
year = {}
}
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Abstract
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single request activates thousands of bitlines in many DRAM chips, only to return a single cache line to the CPU. The focus on cost-per-bit is questionable in modern-day servers where operating costs can easily exceed the purchase cost. Modern technology trends are also placing very different demands on the memory system: (i) queuing delays are a significant component of memory access time, (ii) there is a high energy premium for the level of reliability expected for business-critical computing, and (iii) the memory access stream emerging from multi-core systems exhibits limited locality. All of these trends necessitate an
Keyphrases
energy-constrained multi-cores dram design single request overfetch feature many dram chip business-critical computing memory system significant component multi-core system exhibit limited locality different demand memory access stream modern technology trend queuing delay dram vendor design decision energy penalty prime example purchase cost high energy premium single cache line modern-day server memory access time
