DMCA
Efficient Circuit Clustering for Area and Power Reduction in FPGAs (2002)
| Venue: | In Proceedings of ACM/SIGDA international symposium on Field-programmable gate arrays |
| Citations: | 57 - 0 self |
BibTeX
@INPROCEEDINGS{Singh02efficientcircuit,
author = {Amit Singh and Malgorzata Marek-sadowska},
title = {Efficient Circuit Clustering for Area and Power Reduction in FPGAs},
booktitle = {In Proceedings of ACM/SIGDA international symposium on Field-programmable gate arrays},
year = {2002},
pages = {59--66}
}
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Abstract
We present a routability-driven bottom-up clustering technique for area and power reduction in clustered FPGAs. This technique uses a cell connectivity metric to identify seeds for efficient clustering. Effective seed selection, coupled with an interconnect-resource aware clustering and placement, can have a favorable impact on circuit routability. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 35 % is achieved over previously published results. Power dissipation simulations using a buffered pass-transistor-based FPGA interconnect model are presented. They show that our clustering technique can reduce the overall device power dissipation by an average of 13%. 1.
Keyphrases
power reduction efficient circuit clustering effective seed selection area reduction device utilization overall device power dissipation efficient clustering favorable impact circuit routability cell connectivity buffered pass-transistor-based fpga interconnect model power consumption power dissipation simulation clustered fpgas interconnect-resource aware clustering routability-driven bottom-up clustering technique
