DMCA
Nanowire-based programmable architectures (2005)
| Venue: | ACM Journal on Emerging Technologies in Computing Systems |
| Citations: | 59 - 6 self |
BibTeX
@ARTICLE{Dehon05nanowire-basedprogrammable,
author = {André Dehon},
title = {Nanowire-based programmable architectures},
journal = {ACM Journal on Emerging Technologies in Computing Systems},
year = {2005},
volume = {1},
pages = {109--162}
}
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Abstract
Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.
Keyphrases
nanowire-based programmable architecture bottom-up synthesis technique minimal control regular structure nanowire-based architecture tiny feature pitch nanowires regular array programmable resistance new capability stochastic assembly high density wire crossing atomic dimension mapped-logic density defect-free lithographic fpgas atomic-scale feature size high defect rate
