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Generation of Synthetic Sequential Benchmark Circuits (1997)
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BibTeX
@MISC{Hutton97generationof,
author = {Michael Hutton and Jonathan Rose and Derek Corneil},
title = {Generation of Synthetic Sequential Benchmark Circuits},
year = {1997}
}
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Abstract
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the effectiveness of new architectures and software. Benchmark circuits are a precious commodity, and often cannot be found at the correct granularity, or in the desired quantity. In previous work, we have defined important physical characteristics of combinational circuits. We presented a tool (circ) to extract them, and gave an algorithm and tool (gen) which generates random circuits, parameterized by those characteristics or by a realistic set of defaults. Though a promising first step, only a small portion of real circuits are fully combinational. In this paper we extend the effort to model sequential circuits. We propose new characteristics and generate circuits which are sequential. This allows for the generation of truly useful benchmark circuits, both at and beyond the sizes of nextgeneration FPGAs. By co...
Keyphrases
synthetic sequential benchmark circuit promising first step new characteristic real circuit sequential circuit distinct problem realistic set benchmark circuit new architecture correct granularity random circuit previous work generate circuit useful benchmark circuit small portion commercial circuit fpga vendor nextgeneration fpgas desired quantity precious commodity combinational circuit programmable logic architecture increase important physical characteristic
