BibTeX
@MISC{_optimizationof,
author = {},
title = {Optimization of Simple CPU Core for FPGA M. Be vá},
year = {}
}
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Abstract
Programmable logic arrays (FPGAs) containing CPU core and custom logic present a viable implementation platform for the current generation of embedded systems. This approach offers higher flexibility and lower cost comparing to traditional implementation of separate microcontroller and glue-logic. Important design decision is the choice of the right CPU core. Current market offers large number of CPU cores ranging from tiny 4-bit cores to 32-bit RISC CPUs. These cores are typically compatible with some commercially available microcontroller family. Various clones of the popular Intel 8051 micro are most commonly used. However, experience shows that these cores contain a large legacy overhead and most importantly do not offer a good compilation model for high level languages like Pascal or C. Resulting implementation is either large and inefficient program or difficult to maintain program written in assembly language. A simple 16-bit CPU core called DOP was developed on our department to enhance programmer productivity together with efficiency of implementation on FPGAs. This paper presents discussion of several architectures implementing DOP instruction set and their implementation properties on the current generation of FPGAs. Design of CPU consists of two steps. Instruction Set Architecture (ISA) definition is
Keyphrases
simple cpu core current generation cpu core experience show instruction set architecture available microcontroller family separate microcontroller simple 16-bit cpu core 32-bit risc cpu several architecture right cpu core cpu consists tiny 4-bit core cost comparing programmable logic array high level language large legacy traditional implementation good compilation model popular intel important design decision various clone programmer productivity dop instruction set inefficient program current market offer large number implementation property viable implementation platform custom logic present embedded system
