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UNDERSTANDING AND OPTIMIZING HIGH-SPEED SERIAL MEMORY SYSTEM ARCHITECTURES (2007)
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@MISC{Ganesh07understandingand,
author = {Brinda Ganesh},
title = { UNDERSTANDING AND OPTIMIZING HIGH-SPEED SERIAL MEMORY SYSTEM ARCHITECTURES},
year = {2007}
}
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Abstract
Performance improvements in memory systems have traditionally been obtained by scaling data bus width and speed. Maintaining this trend while continuing to satisfy memory capacity demands of server systems is challenging due to the electrical constraints posed by high-speed parallel buses. To satisfy the dual needs of memory bandwidth and memory system capacity, new memory system protocols have been proposed by the leaders in the memory system industry. These protocols replace the conventional memory bus interface between the memory controller and the memory modules with narrow, high-speed, uni-directional point-to point interfaces. The memory controller communicates with the memory modules using a packet-based protocol, which is trans-lated to the conventional DRAM commands at the memory modules. Memory latency has been widely accepted as one of the key performance bottlenecks in computer architecture. Hence, any changes to memory sub-system architecture and protocol can have a significant impact on overall system performance. In the first part of this dissertation, we did an extensive study and analysis of how the behavior of newly proposed memory architecture to iden-tify clearly how it impacts memory sub-system performance and what the key performance limiters are. We then went on to use the insights we gained from this analysis to propose two optimization
Keyphrases
memory module memory controller key performance limiter first part memory system memory sub-system performance computer architecture high-speed parallel bus sub-system architecture significant impact electrical constraint key performance bottleneck memory architecture packet-based protocol server system extensive study data bus width conventional dram command memory latency memory bandwidth performance improvement memory capacity demand overall system performance new memory system protocol uni-directional point-to point interface memory system capacity conventional memory bus interface memory system industry dual need
