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Unbounded Transactional Memory (2005)
| Citations: | 261 - 8 self |
BibTeX
@INPROCEEDINGS{Ananian05unboundedtransactional,
author = {C. Scott Ananian and Krste Asanović and Bradley C. Kuszmaul and Charles E. Leiserson and Sean Lie},
title = {Unbounded Transactional Memory},
booktitle = {},
year = {2005},
pages = {316--327}
}
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Abstract
Background: Programming in a shared-memory environment often requires the use of atomic regions for program correctness. Traditionally, atomicity is achieved through critical sections protected by locks. Unfortunately, locks are very difficult to program with since they introduce problems such as deadlock and priority inversion. Locks also introduce a significant performance overhead since locking instructions are expensive and performing deadlock avoidance can be slow. In addition, locks are simply memory locations so there is an added space overhead associated with locking as well. Hardware Transactions: To overcome the problems with locks, Herlihy and Moss proposed a hardware transactional memory (HTM) [1] scheme that gives the programmer a more intuitive atomicity primitive, a transaction. A transaction is an atomic region that either completes atomically or fails and has no effect on the global memory state. Two regions are atomic if, after they are run, they can viewed as having run in some serial order with no interleaved instructions. HTM ensures atomicity by simply running the atomic region speculatively. If no other processor accesses any of the same memory locations as the atomic region, the speculative state can be committed since atomicity has been satisfied. On the other hand, HTM must provide the mechanism to detect conflicting memory accesses if they do occur. In such a case, HTM will abort all the
Keyphrases
atomic region transactional memory memory location serial order priority inversion shared-memory environment intuitive atomicity primitive significant performance overhead added space overhead hardware transactional memory memory access critical section hardware transaction global memory state interleaved instruction deadlock avoidance program correctness speculative state
