Dual-core execution: building a highly scalable single-thread instruction window

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Dual-core execution: building a highly scalable single-thread instruction window (2005)

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by Huiyang Zhou

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@MISC{Zhou05dual-coreexecution:,
    author = {Huiyang Zhou},
    title = {Dual-core execution: building a highly scalable single-thread instruction window},
    year = {2005}
}

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Abstract

Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thread performance is not addressed. In this paper, we propose a new execution paradigm that utilizes multi-cores on a single chip collaboratively to achieve high performance for single-thread memoryintensive workloads while maintaining the flexibility to support multithreaded applications. The proposed execution paradigm, dual-core execution, consists of two superscalar cores (a front and back processor) coupled with a queue. The front processor fetches and preprocesses instruction streams and retires processed instructions into the queue for the back processor to consume. The front processor executes instructions as usual except for cache-missing loads, which produce an invalid value instead of blocking the pipeline. As a result, the front processor runs far ahead to warm up the data caches and fix branch mispredictions for the back processor. In-flight instructions are distributed in the front processor, the queue, and the back processor, forming a very large instruction window for single-thread out-oforder execution. The proposed architecture incurs only minor hardware changes and does not require any large centralized structures such as large register files, issue queues, load/store queues, or reorder buffers. Experimental results show remarkable latency hiding capabilities of the proposed architecture, even outperforming more complex single-thread processors with much larger instruction windows than the front or back processor. 1.

Keyphrases

dual-core execution back processor scalable single-thread instruction window front processor reorder buffer large register file issue queue remarkable latency fix branch mispredictions load store queue single-thread performance superscalar core single-thread memoryintensive workload instruction window invalid value cache-missing load proposed execution paradigm high performance large instruction window front processor fetch multithreaded application data cache preprocesses instruction stream single chip system throughput new execution paradigm minor hardware change current integration trend multi-core processor complex single-thread processor large centralized structure single-thread out-oforder execution in-flight instruction experimental result proposed architecture single-chip multi-core processor

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