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Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
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@MISC{Mutlu_stall-timefair,
author = {Onur Mutlu and et al.},
title = {Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors},
year = {}
}
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Abstract
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory access scheduling techniques try to optimize the overall data throughput obtained from the DRAM and thus do not take into account inter-thread interference. Therefore, different threads running together on the same chip can experience extremely different memory system performance: one thread can experience a severe slowdown or starvation while another is unfairly prioritized by the memory scheduler. This paper proposes a new memory access scheduler, called the Stall-Time Fair Memory scheduler (STFM), that provides quality of service to different threads sharing the DRAM memory system. The goal of the proposed scheduler is to “equalize ” the DRAM-related slowdown experienced by each thread due to interference from other threads, without hurting overall system performance. As such, STFM takes into account inherent memory characteristics of each thread and does not unfairly penalize threads that use the DRAM system without interfering with other threads. We show that STFM significantly reduces the unfairness in the DRAM system while also improving system throughput (i.e., weighted speedup of threads) on a wide variety of workloads and systems. For example, averaged over 32 different workloads running on an 8-core CMP, the ratio between the highest DRAM-related slowdown and the lowest DRAM-related slowdown reduces from 5.26X to 1.4X, while the average system throughput improves by 7.6%. We qualitatively and quantitatively compare STFM to one new and three previouslyproposed memory access scheduling algorithms, including network fair queueing. Our results show that STFM provides the best fairness, system throughput, and scalability.
Keyphrases
chip multiprocessor different thread stall-time fair memory access scheduling system throughput dram-related slowdown dram system dram-related slowdown reduces compare stfm account inter-thread interference new memory access scheduler dram memory dram memory system average system throughput improves different workload 8-core cmp network fair queueing memory access severe slowdown previouslyproposed memory access account inherent memory characteristic overall data throughput memory request major resource stall-time fair memory scheduler different memory system performance overall system performance memory scheduler wide variety
