Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

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Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008)

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by Onur Mutlu, et al.

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136 - 48 self

BibTeX

@MISC{Mutlu08parallelism-awarebatch,
    author = {Onur Mutlu and et al.},
    title = {Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems},
    year = {2008}
}

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Abstract

In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by causing bank/bus/row-buffer conflicts but they can also destroy other threads’ DRAM-bank-level parallelism. Requests whose latencies would otherwise have been overlapped could effectively become serialized. As a result both fairness and system throughput degrade, and some threads can starve for long time periods. This paper proposes a fundamentally new approach to designing a shared DRAM controller that provides quality of service to threads, while also improving system throughput. Our parallelism-aware batch scheduler (PAR-BS) design is based on two key ideas. First, PAR-BS processes DRAM requests in batches to provide fairness and to avoid starvation of requests. Second, to optimize system throughput, PAR-BS employs a parallelism-aware DRAM scheduling policy that aims to process requests from a thread in parallel in the DRAM banks, thereby reducing the memory-related stall-time experienced by the thread. PAR-BS seamlessly incorporates support for system-level thread priorities and can provide different service levels, including purely opportunistic service, to threads with different priorities. We evaluate the design trade-offs involved in PAR-BS and compare it to four previously proposed DRAM scheduler designs on 4-, 8-, and 16-core systems. Our evaluations show that, averaged over 100 4-core workloads, PAR-BS improves fairness by 1.11X and system throughput by 8.3 % compared to the best previous scheduling technique, Stall-Time Fair Memory (STFM) scheduling. Based on simple request prioritization rules, PAR-BS is also simpler to implement than STFM.

Keyphrases

shared dram system parallelism-aware batch scheduling dram system system throughput system throughput degrade simple request prioritization rule dram controller design trade-off new approach stall-time fair memory row-buffer conflict parallelism-aware batch scheduler 16-core system parallelism-aware dram scheduling policy dram bank dram scheduler design previous scheduling technique key idea different service level memory-related stall-time opportunistic service different priority thread dram-bank-level parallelism 4-core workload long time period system-level thread priority dram request