Abstract

Abstract — A simple yet realistic MOS model, namely the a-power law MOS model, is introduced to include the carrier velocity saturation effect, which becomes eminent in short-channel MOSFET’S. The model is an extension of Shockley’s square-law MOS model in the saturation region. Since the model is simple, it can be applied for handling MOSFET circuits analytically and can predict the circuit behavior in the submicro-meter region. Using the model, closed-form expressions are derived for the delay, the short-circuit power, and the transition voltage of CMOS invert-ers. The resultant delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is concluded that the CMOS inverter delay becomes less sensitive to the input waveform slope and short-circuit dksipation increases as the earner velocity saturation effects get severer in short-channel MOSFET’S. 1.