DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design

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DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design (1999)

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by Todd M. Austin

Venue:	In Proc. 32nd Annual Intl. Symp. on Microarchitecture
Citations:	374 - 15 self

BibTeX

@INPROCEEDINGS{Austin99diva:a,
    author = {Todd M. Austin},
    title = {DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design},
    booktitle = {In Proc. 32nd Annual Intl. Symp. on Microarchitecture},
    year = {1999},
    pages = {196--207}
}

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Abstract

Building a high-petformance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To&rther complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation interference. In this paper; we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. Thefunctional checker verifies the correctness of the core processor’s computation, only permitting correct results to commit. Overall design cost can be dramatically reduced because designers need only veri ’ the correctness of the checker unit. We detail the DIVA checker architecture, a design optimized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA checkers have little impact on core processor peflormance. To make the case for reduced verification costs, we argue that the DIVA checker should lend itself to functional and electrical verification better than a complex core processor Finally, future applications that leverage dynamic veri@cation to increase processor performance and availability are suggested. 1

Keyphrases

reliable substrate deep submicron microarchitecture design many reliability challenge complex core processor finally processor performance checker unit commit phase future application little impact resource-frugal diva checker overall design cost microprocessor design processor pipeline large complex system correct result novel microarchitectural technique core processor computation high-petformance microprocessor functional checker unit thefunctional checker reduced verification cost operating condition logic failure dynamic verification diva checker low cost construct implementation detailed timing simulation core processor peflormance electrical verification natural radiation interference dynamic veri cation degraded signal quality diva checker architecture

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