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Area-efficient instruction set synthesis for reconfigurable system-on-chip designs (2004)
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| Venue: | In Proceedings of the Design Automation Conference (DAC |
| Citations: | 21 - 2 self |
BibTeX
@INPROCEEDINGS{Brisk04area-efficientinstruction,
author = {Philip Brisk and Adam Kaplan and Majid Sarrafzadeh},
title = {Area-efficient instruction set synthesis for reconfigurable system-on-chip designs},
booktitle = {In Proceedings of the Design Automation Conference (DAC},
year = {2004},
pages = {395--400}
}
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Abstract
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these compilers produce hardware that is larger than necessary, as they do not allow instructions to share hardware resources. This study presents an efficient heuristic which transforms a set of custom instructions into a single hardware datapath on which they can execute. Our approach is based on the classic problems of finding the longest common subsequence and substring of two (or more) sequences. This heuristic produces circuits which are as much as 85.33 % smaller than those synthesized by integer linear programming (ILP) approaches which do not explore resource sharing. On average, we obtained 55.41 % area reduction for pipelined datapaths, and 66.92 % area reduction for VLIW datapaths. Our solution is simple and effective, and can easily be integrated into an existing silicon compiler.
Keyphrases
reconfigurable system-on-chip design area-efficient instruction area reduction silicon compiler common subsequence share hardware resource vliw datapaths single hardware datapath efficient heuristic integer linear programming classic problem custom instruction field programmable gate array pipelined datapaths
