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Instruction Generation and Regularity Extraction for Reconfigurable Processors (2002)
| Venue: | In CASES |
| Citations: | 43 - 4 self |
BibTeX
@INPROCEEDINGS{Brisk02instructiongeneration,
author = {Philip Brisk and Adam Kaplan and Ryan Kastner and Majid Sarrafzadeh},
title = {Instruction Generation and Regularity Extraction for Reconfigurable Processors},
booktitle = {In CASES},
year = {2002},
pages = {262--269}
}
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Abstract
The increasing demand for complex and specialized embedded hardware must be met by processors which are optimized for performance, yet are also extremely flexible. In our work, we explore the tradeoff between flexibility and performance in the domain of reconfigurable processor design. Specifically, we seek to identify regularly occurring, computation-heavy patterns in an application or set of applications. These patterns become candidates for hard-logic implementation, potentially embedded in the flexible reconflgurable fabric as special optimized instructions. In this work we present an extension to previous work in instruction generation: an algorithm that identifies parallel templates. We discuss the advantages of parallel templates, and prove the correctness of our algorithm. We introduce an All-Pairs Common Slack Graph (APCSG) as an effective tool for parallel template generation. Finally, we demonstrate the effectiveness of our algorithm on several applications' dataflow graphs, reducing latency on average by 51.98%, without unreasonably increasing chip area.
Keyphrases
instruction generation reconfigurable processor regularity extraction parallel template flexible reconflgurable fabric several application hard-logic implementation previous work special optimized instruction computation-heavy pattern parallel template generation embedded hardware chip area dataflow graph effective tool reconfigurable processor design all-pairs common slack graph
