BibTeX
@MISC{Hsieh90lib:a,
author = {Yung-Ching Hsieh},
title = {LiB: A Cell Layout Generator },
year = {1990}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
We present an automatic layout generation system, called LiB. for the library cells used in CMOS ASIC design LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. Our layout style is similar to that proposed by Uehara and van Cleemput in [17]. We propose several heuristic algorithms to solve the transistor-clustering,-pairing,-chaining,-folding, the chain placement, the routing, and the net assign-ment problems, respectively. Experimental results are presented to show the capability of LiB.
