@MISC{Cache74cpu:, author = {L Cache}, title = {CPU:}, year = {1774}}
FPU: Integrated CPU(s) enabled: 1 core, 1 chip, 1 core/chip(Hyper-Threading Technology Disabled) CPU(s) orderable: 1 Parallel: No Primary Cache: 12k micro-ops I + 16KBD on chip
core chip hyper-threading technology disabled primary cache