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3
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ProtoFlex: Towards Scalable, FullSystem Multiprocessor Simulations Using FPGAs
– Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai
- 2009
|
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4
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ProtoFlex: Co-Simulation for Component-wise FPGA Emulator Development
– Eric S. Chung, James C. Hoe, Babak Falsafi
- 2006
|
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20
|
RAMP: Research Accelerator for Multiple Processors
– John Wawrzynek, Mark Oskin, Christoforos Kozyrakis, Derek Chiou, David A. Patterson, Shih-lien Lu, James C. Hoe, Krste Asanovic
- 2006
|
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9
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UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development
– David August, Jonathan Chang, Sylvain Girbal, Daniel Gracia-perez, Gilles Mouchard, David Penry, Neil Vachharajani
- 2007
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This work is supported in part by the National Science Foundation,
– With Grants Eia-, Carl J. Mauer, Mark D. Hill, David A. Wood
- 2002
|
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56
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Full-System Timing-First Simulation
– Carl J. Mauer, Mark D. Hill, David A. Wood
- 2002
|
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1
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ArchExplorer.org: Joint Compiler/Hardware Exploration for Fair Comparison of Architectures
– Veerle Desmet, Sylvain Girbal, Olivier Temam
|
|
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COREMU: A Scalable and Portable Parallel Full-system Emulator
– Zhaoguo Wang, Ran Liu, Yufei Chen, Xi Wu, Haibo Chen, Bingyu Zang, Zhaoguo Wang, Ran Liu, Yufei Chen, Xi Wu, Haibo Chen, Bingyu Zang
- 2010
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BREAKING THE MEMORY WALL FOR HIGHLY MULTI-THREADED CORES
– Kevin Skadron, John Lach, Kim Hazelwood, Jason Lawrence, Nathan Binkert, James H. Aylor (dean
- 2010
|
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3
|
Parallelization of IBM mambo system simulator in functional modes
– Kun Wang, Yu Zhang, Xiaowei Shen, Huayong Wang
- 2008
|
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1
|
A Desktop Computer with a Reconfigurable Pentium râ—‹
– Shih-lien L. Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow
|
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15
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TCP offload through connection handoff
– Hyong-youb Kim, Scott Rixner
- 2006
|
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6
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Performance analysis of system overheads in TCP/IP workloads
– Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, Steven K. Reinhardt
- 2005
|
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Preprint: To Appear in MICRO 2007. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
– Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart, D. Eric Johnson, Jebediah Keefe, Hari Angepat
|
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10
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FPGA-based Fast, Cycle-Accurate, Full-System Simulators
– Derek Chiou, Huzefa Sunjeliwala, Dam Sunwoo, John Xu, Nikhil Patil
- 2006
|
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14
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GARNET: a detailed onchip network model inside a full-system simulator
– Niket Agarwal, Tushar Krishna, Li-shiuan Peh, Niraj K. Jha
|
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unknown title
– D. Burke
|
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2
|
Improving instruction cache performance in OLTP
– Stavros Harizopoulos, Anastassia Ailamaki
- 2006
|
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3
|
Store-ordered streaming of shared memory
– Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, Babak Falsafi
- 2005
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