A Set of Benchmarks for Modular Testing of SOCs (2002)

by Erik Jan Marinissen , Vikram Iyengar , Krishnendu Chakrabarty
Venue:ITC'02
Citations:39 - 17 self

Active Bibliography

4 Recent Advances in Test Planning for Modular Testing of Core-Based SOCs – Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen, Ibm Microelectronics - 2002
11 Efficient Test Solutions for Core-based Designs – Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng, Senior Member - 2004
31 Optimal Test Access Architectures for System-on-a-Chip – Krishnendu Chakrabarty - 2001
An Integrated Framework for the Design . . . – Erik Larsson, Zebo Peng - 2002
54 Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip – Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling – Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty - 2009
1 Addressing Useless Test Data in Core-Based System-on-a-Chip Test – Paul T. Gonciari, Bashir M. Al-hashimi, Nicola Nicolici, Paul T. Gonciari, Bashir M. Al-hashimi, Nicola Nicolici
9 On Using IEEE P1500 SECT for Test Plug-n-Play – Erik Jan Marinissen, Rohit Kapur, Yervant Zorian - 2000
1 Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs – Anuja Sehgal, Krishnendu Chakrabarty, Senior Member
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints – Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga
1 Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm – Haidar M. Harmanani, Hassan A - 2006
6 System-on-a-Chip Test Scheduling with Precedence Relationships, Preemption, and Power Constraints – Vikram Iyengar, Krishnendu Chakrabarty - 2002
35 Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming – Krishnendu Chakrabarty - 2000
6 Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip – Vikram Iyengar, Krishnendu Chakrabarty - 2001
12 Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization – Sandeep Kumar Goel, Erik Jan Marinissen - 2003
3 Efficient Test Access Mechanism Optimization for System-on-Chip – Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen - 2003
22 On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization – Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen - 2002
Test Planning and Design Space Exploration in a Core-based Environment – Erika Cota Luigi - 2002
6 The Design and Optimization of SOC Test Solutions – Erik Larsson, Zebo Peng, Gunnar Carlsson - 2001