Active Bibliography

1 Maximizing Area Efficiency for SingleChip Server – Jaehyuk Huh, Doug Burger, Stephen W. Keckler - 2001
7 Using Compression to Improve Chip Multiprocessor Performance – Alaa R. Alameldeen - 2006
20 High-Performance DRAMs in Workstation Environments – Vinodh Cuppu, Bruce Jacob, Brian Davis, Trevor Mudge - 2001
General-Purpose Architectures for Media Processing and Database Workloads – Parthasarathy Ranganathan - 2000
7 A Case for Shared Instruction Cache on Chip Multiprocessors running OLTP – Partha Kundu, Murali Annavaram, Trung Diep, John Shen - 2004
August, 2000General-Purpose Architectures for Media Processing and Database Workloads – Parthasarathy Ranganathan, Parthasarathy Ranganathan, D. Cooper, Willy E. Zwaenepoel, Parthasarathy Ranganathan
24 Scaling and Characterizing Database Workloads: Bridging the Gap between Research and Practice – Richard Hankins, Trung Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John P. Shen - 2003
74 Reducing DRAM latencies with an integrated memory hierarchy design – Wei-fen Lin, Steven K. Reinhardt, Doug Burger - 2001
2 Cache Memory Design Trade-offs for Current and Emerging Workloads – Martin Karlsson - 2003
105 Measuring Experimental Error in Microprocessor Simulation – Rajagopalan Desikan, Doug Burger, Stephen W. Keckler - 2001
4 Cooperative hardware/software caching for next-generation memory systems – Zhenlin Wang, Charles C. Weems, J. Eliot, B. Moss, Csaba Andras Moritz, Doug Burger Member - 2003
Hardware Optimizations Enabled by a Decoupled Fetch Architecture – Glenn Reinman - 2001
13 Master/Slave Speculative Parallelization and Approximate Code – Craig B. Zilles - 2002
Exploring Design Alternatives for a Highly-Integrated, Wide-Issue, Microprocessor-Based System – David H. Albonesi, Israel Koren
175 Piranha: A scalable architecture based on single-chip multiprocessing – Luiz André Barroso, Kourosh Gharachorloo, Robert Mcnamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese - 2000
Efficient data organization and management on – Minglong Shao, Greg Ganger, Todd Mowry - 2008
18 Code Layout Optimizations for Transaction Processing Workloads – Alex Ramirez, Luiz André Barroso , Kourosh Gharachorloo , Robert Cohn , Josep Larriba-pey, P. Geoffrey Lowney , Mateo Valero - 2001
27 A Performance Comparison of DRAM Memory System Optimizations for SMT Processors – Zhichun Zhu - 2005
38 The stampede approach to thread-level speculation – J. Gregory Steffan, Christopher Colohan, Antonia Zhai, Todd C. Mowry - 2005