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## Booledozer: Logic synthesis for ASICs (1996)

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Venue: | IBM Journal of Research and Development |

Citations: | 19 - 3 self |

### Citations

444 |
Logic Minimization Algorithms for VLSI Synthesis
- Brayton, Hachtel, et al.
- 1984
(Show Context)
Citation Context ...t 100 000 gates) than the current industry practice. That implies not only an e cient database, but also e cient algorithms. BooleDozer relies on compiler-like analysis techniques more than two-level =-=[2, 3]-=- or Binary Decision Diagrams (BDD) [4] based techniques, whose performance degrades too quickly with increasing problem size. The second requirement is openness of all interfaces, which means that loc... |

366 |
Graph based algorithms for Boolean function manipulation
- Bryant
- 1986
(Show Context)
Citation Context ...y practice. That implies not only an e cient database, but also e cient algorithms. BooleDozer relies on compiler-like analysis techniques more than two-level [2, 3] or Binary Decision Diagrams (BDD) =-=[4]-=- based techniques, whose performance degrades too quickly with increasing problem size. The second requirement is openness of all interfaces, which means that local support people can write special pu... |

268 | A survey of power estimation techniques in VLSI circuits
- Najm
- 1994
(Show Context)
Citation Context ...rage energy consumption per cycle is computed for each net and is used to guide transformations toward lower power consumption. Switching activity can also be estimated using a probabilistic approach =-=[10]-=-. BooleDozer avoided this because it requires functional evaluation at each gate, which could be very expensive. Furthermore, temporal and spatial correlations of input signals are di cult to account ... |

210 |
MIS: A Multiple-Level Logic Optimization System.”
- Brayton, Rudell, et al.
- 1987
(Show Context)
Citation Context ...zer logic synthesis system designed to serve the design community at IBM. Its design draws on the experience from the previous IBM internal synthesis tools[5,6]aswell as from external synthesis tools =-=[2, 7, 8]-=-. BooleDozer is the result of a joint project between IBM Yorktown Research, IBM Advanced Workstation Division, and IBM Microelectronics Division. This has led to a powerful and customizable logic syn... |

155 | DAGON: Technology Binding and Local Optimization by DAG Matching,”
- Keutzer
- 1987
(Show Context)
Citation Context ... technologydependent gates from a prescribed library of primitives. The various approaches to this mapping problem can be broadly divided into four categories: rule-based mapping [19], graph matching =-=[20]-=-, direct mapping [21] and functional matching [22]. Technology mapping in BooleDozer uses a combination of all four approaches and divides the mapping process into two separate phases: the matching ph... |

153 |
Veri cation of Large Synthesized Designs",
- Brand
- 1993
(Show Context)
Citation Context ... S computes a function f. If f is replaced by a di erent function g, will that change the functionality F of the whole design?" This question is asked in transduction, redundancy removal, veri cation =-=[41]-=-, and incremental synthesis [42]. To answer this question in general, we use the following lemma. Lemma 1 : F (f) =F (g) i F (f g) =F (0); F (f) =F (g) i F (f g) =F (1). The expression F (f g) represe... |

97 |
The map method for synthesis of combinational logic circuits
- Karnaugh
- 1953
(Show Context)
Citation Context ...ented. A crucial consideration is the size of this representation; as design size grows, more and more compact representations are required. Originally Boolean reasoning was performed on truth tables =-=[32]-=-. Since the size of a truth table is guaranteed to be exponential in the number of input variables, truth tables were replaced bytwo-level representations [33]. Atwo-level representation tends to be s... |

78 |
D.D.: Timing analysis of computer hardware.
- Hitchcock, Smith, et al.
- 1982
(Show Context)
Citation Context ...e whether the circuit has met the timing speci cations. Circuit simulation provides accuracy but is infeasible for determining the delays in a large network. EinsTimer provides static timing analysis =-=[11, 12]-=- as an integral part of BooleDozer. In static timing analysis, we ignore the function of the design and consider only the possible timing relationships within it. In doing so, we always consider the w... |

70 |
Critical path tracing: An alternative to fault simulation
- Abramovici, Menon, et al.
- 1984
(Show Context)
Citation Context ...opagation type questions. However, fault simulation may take time proportional to the size of the design, which tends to be too slow. Therefore, BooleDozer sometimes uses approximate fault simulation =-=[43]-=-, which may give us an a rmative answer in constant time. However, in contrast to good-machine simulation, approximate fault simulation may err on either sides; therefore, an a rmative answer given by... |

63 | MINI: A Heuristic Approach for Logic Minimization,”
- Hong, Cain, et al.
- 1974
(Show Context)
Citation Context ...t 100 000 gates) than the current industry practice. That implies not only an e cient database, but also e cient algorithms. BooleDozer relies on compiler-like analysis techniques more than two-level =-=[2, 3]-=- or Binary Decision Diagrams (BDD) [4] based techniques, whose performance degrades too quickly with increasing problem size. The second requirement is openness of all interfaces, which means that loc... |

59 |
Chortle: A Technology Mapping Program for Lookup Table-Based FieldProgrammable Gate Arrays,"
- Francis, Rose, et al.
- 1990
(Show Context)
Citation Context ...rrive sooner if inverting gates are faster than noninverting gates in this technology. 28s5.11 FPGA technology mapping Technology mapping for FPGAs can be performed by FPGA speci c technology mappers =-=[25, 26]-=- or by using library-based technology mappers [20]. BooleDozer provides both FPGA speci c and library-based technology mappers for FPGAs. BooleDozer provides FPGA speci c mapping for any FPGA technolo... |

54 | Multi-Level Logic Optimization by Implication Analysis”,
- Kunz, Pradhan
- 1994
(Show Context)
Citation Context ...st generator [35, 36], which operates on a gate network, thus avoiding the problems of 32sother existing representations. It has been shown that there is no theoretical loss in using a test generator =-=[37]-=-; any network can be transformed to any equivalent network by transformations, which do no Boolean reasoning except to ask the test generator whether or not certain faults are testable. While in theor... |

51 |
The Transduction Method-Design of Logic Networks Based on Permissible Functions,”
- Muroga
- 1989
(Show Context)
Citation Context ...to connect S. This transformation is performed during technology-independent optimization to reduce estimated area, but also 21stends to have a bene cial e ect on delay. 5.4 Transduction Transduction =-=[18]-=- replaces some functions with other, more e cient ones. For example, in Figure 13 the function of S can be replaced by C _D, because that is a so called \permissible function" for the original functio... |

51 |
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications,
- McGeer, Brayton
- 1991
(Show Context)
Citation Context ...he implication is false; if the test generator can prove that there is no such input pattern, the implication is true. Justi cation questions are used in selector generation [38], false path analysis =-=[39, 40]-=-, and other synthesis tasks. Before using the test generator, BooleDozer performs good-machine simulation of the whole design. The number of patterns is a parameter, which is discussed later. The obje... |

43 |
Complexity of lookup-table minimization problem for FPGA technology mapping
- Farrahi, Sarrafzadeh
- 1994
(Show Context)
Citation Context ...rrive sooner if inverting gates are faster than noninverting gates in this technology. 28s5.11 FPGA technology mapping Technology mapping for FPGAs can be performed by FPGA speci c technology mappers =-=[25, 26]-=- or by using library-based technology mappers [20]. BooleDozer provides both FPGA speci c and library-based technology mappers for FPGAs. BooleDozer provides FPGA speci c mapping for any FPGA technolo... |

36 |
Introduction to the Theory of Switching Circuits,
- McCluskey
- 1965
(Show Context)
Citation Context ... reasoning was performed on truth tables [32]. Since the size of a truth table is guaranteed to be exponential in the number of input variables, truth tables were replaced bytwo-level representations =-=[33]-=-. Atwo-level representation tends to be smaller than a truth table, but its size may also grow exponentially. Therefore, instead of representing the whole function in two levels, the function can be p... |

34 |
Technology Mapping in MIS”,
- DETJENS, GANNOT, et al.
- 1987
(Show Context)
Citation Context ...zer logic synthesis system designed to serve the design community at IBM. Its design draws on the experience from the previous IBM internal synthesis tools[5,6]aswell as from external synthesis tools =-=[2, 7, 8]-=-. BooleDozer is the result of a joint project between IBM Yorktown Research, IBM Advanced Workstation Division, and IBM Microelectronics Division. This has led to a powerful and customizable logic syn... |

33 |
Technology Mapping using Boolean Matching and Don’t Care Sets”,
- MAILHOT, MICHELI
- 1990
(Show Context)
Citation Context ...ry of primitives. The various approaches to this mapping problem can be broadly divided into four categories: rule-based mapping [19], graph matching [20], direct mapping [21] and functional matching =-=[22]-=-. Technology mapping in BooleDozer uses a combination of all four approaches and divides the mapping process into two separate phases: the matching phase and the covering phase. Matching is the identi... |

31 | SOCRATES: A system for automatically synthesizing and optimizing combinational logic
- Gregory, Bartlett, et al.
- 1986
(Show Context)
Citation Context ...target network, using technologydependent gates from a prescribed library of primitives. The various approaches to this mapping problem can be broadly divided into four categories: rule-based mapping =-=[19]-=-, graph matching [20], direct mapping [21] and functional matching [22]. Technology mapping in BooleDozer uses a combination of all four approaches and divides the mapping process into two separate ph... |

29 |
Logic synthesis through local transformations
- Darringer, Joyner, et al.
- 1981
(Show Context)
Citation Context ... The rest of this paper describes the BooleDozer logic synthesis system designed to serve the design community at IBM. Its design draws on the experience from the previous IBM internal synthesis tools=-=[5,6]-=-aswell as from external synthesis tools [2, 7, 8]. BooleDozer is the result of a joint project between IBM Yorktown Research, IBM Advanced Workstation Division, and IBM Microelectronics Division. This... |

27 |
LSS: A system for Production Logic Synthesis.
- Darringer, Brand, et al.
- 1984
(Show Context)
Citation Context ... The rest of this paper describes the BooleDozer logic synthesis system designed to serve the design community at IBM. Its design draws on the experience from the previous IBM internal synthesis tools=-=[5,6]-=-aswell as from external synthesis tools [2, 7, 8]. BooleDozer is the result of a joint project between IBM Yorktown Research, IBM Advanced Workstation Division, and IBM Microelectronics Division. This... |

20 | Incremental Synthesis".
- Brand, Drumm, et al.
- 1994
(Show Context)
Citation Context ...s replaced by a di erent function g, will that change the functionality F of the whole design?" This question is asked in transduction, redundancy removal, veri cation [41], and incremental synthesis =-=[42]-=-. To answer this question in general, we use the following lemma. Lemma 1 : F (f) =F (g) i F (f g) =F (0); F (f) =F (g) i F (f g) =F (1). The expression F (f g) represents a replacement of a subfuncti... |

19 |
Timing Analysis Using Functional Analysis,”
- Brand, Iyengar
- 1988
(Show Context)
Citation Context ...state transitions, converting the problem which requires exponential time to one which can be done in linear time. The drawback of static timing analysis is that the critical paths may be false paths =-=[13]-=-, causing the performance of the design to be underestimated. However, recent experiments [14] have shown that when su cient don't-care information is used in 13ssynthesis, timing critical paths are r... |

14 |
A small Test Generator for Large Designs”,
- KUNDU, HUISMAN, et al.
- 1992
(Show Context)
Citation Context ...been replaced by BDDs. While BDDs tend to be more compact, they still may grow exponentially with the size of the network. Therefore, in BooleDozer, Boolean reasoning is performed by a test generator =-=[35, 36]-=-, which operates on a gate network, thus avoiding the problems of 32sother existing representations. It has been shown that there is no theoretical loss in using a test generator [37]; any network can... |

10 |
Speed up of Test Generation using High Level Primitives”,
- KUNDA, NARAIN, et al.
- 1990
(Show Context)
Citation Context ...been replaced by BDDs. While BDDs tend to be more compact, they still may grow exponentially with the size of the network. Therefore, in BooleDozer, Boolean reasoning is performed by a test generator =-=[35, 36]-=-, which operates on a gate network, thus avoiding the problems of 32sother existing representations. It has been shown that there is no theoretical loss in using a test generator [37]; any network can... |

7 |
Mattheyses, \A Linear Time Heuristic for Improving Network Partitions
- M, Fiduccia, et al.
- 1982
(Show Context)
Citation Context ...pecial transformation has been added to BooleDozertoprovide an e cient method to partition a design. The underlying algorithm of the partitioner is based on a linear time graph partitioning heuristic =-=[30]-=-. The BooleDozer partitioner uses a novel multistep partitioning process [31] which is geared toward minimizing both the number of the segments and the total number of I/O pins in the resulting partit... |

6 |
High-level synthesis in an industrial environment,”
- Bergamaschi, O'Connor, et al.
- 1995
(Show Context)
Citation Context ...HDL or Verilog. The behavior of this description is checked using simulation. The high-level design is compiled into a register-transfer-level (RTL) network by a behavioral synthesis tool such as HIS =-=[1]-=-. The RTL network is composed of equation blocks, functional blocks such as adders and multiplexors, and primitive gates. The RTL network is the input to logic synthesis. To illustrate this process, a... |

6 |
Mapping Properties of Multi-level Logic Synthesis
- Lega
- 1988
(Show Context)
Citation Context ...gates from a prescribed library of primitives. The various approaches to this mapping problem can be broadly divided into four categories: rule-based mapping [19], graph matching [20], direct mapping =-=[21]-=- and functional matching [22]. Technology mapping in BooleDozer uses a combination of all four approaches and divides the mapping process into two separate phases: the matching phase and the covering ... |

4 |
In the Driver's Seat of BooleDozer
- Brand, Damiano, et al.
- 1994
(Show Context)
Citation Context ...it becomes gradually more di cult to improve thetiming. To allow the designer to control the running time, special commands are provided in the scripting language to run for a particular amount oftime=-=[9]-=-. Not only critical paths are important during timing correction; working on noncritical 9slogic can improve the overall performance of the design. Slowing down a noncritical path, thereby reducing th... |

4 |
Don't Cares in Synthesis: Theoretical Pitfalls and Practical Solutions
- Brand, Bergamaschi, et al.
- 1995
(Show Context)
Citation Context ...done in linear time. The drawback of static timing analysis is that the critical paths may be false paths [13], causing the performance of the design to be underestimated. However, recent experiments =-=[14]-=- have shown that when su cient don't-care information is used in 13ssynthesis, timing critical paths are rarely false. Timing analysis is conceptually performed on a directed graph of the network. To ... |

3 |
Timing Veri cation and the Timing Analysis Program
- Sr
- 1982
(Show Context)
Citation Context ...e whether the circuit has met the timing speci cations. Circuit simulation provides accuracy but is infeasible for determining the delays in a large network. EinsTimer provides static timing analysis =-=[11, 12]-=- as an integral part of BooleDozer. In static timing analysis, we ignore the function of the design and consider only the possible timing relationships within it. In doing so, we always consider the w... |

3 |
Multi-Level Logic Simpli cation using Don't Cares and Filters
- Saldanha, Wang, et al.
- 1989
(Show Context)
Citation Context ... the function, the rest of the function is represented in the form of \don't cares." Since the two level don't care representation also grows exponentially, not all of the function can be represented =-=[34]-=-. Therefore, two-level representations have been replaced by BDDs. While BDDs tend to be more compact, they still may grow exponentially with the size of the network. Therefore, in BooleDozer, Boolean... |

2 |
PLA-Based Synthesis Without PLAs
- Brand
- 1989
(Show Context)
Citation Context ...tes on the input cone of P and extracts the function Q. The word \kernel" is usually used in the context of two-level logic representation, but BooleDozer performs kernel factoring on multilevel logic=-=[16]-=-. In multilevel logic, kernel factoring becomes a specialized form of Shannon expansion; for example, in Figure 11, Shannon expansion was done using the net C. Kernel factoring is used during technolo... |

2 |
Global ow optimization in automatic logic design
- Berman, Tervillyan
- 1991
(Show Context)
Citation Context ...n Figure 11, Shannon expansion was done using the net C. Kernel factoring is used during technology-independent optimization to reduce estimated area. 5.3 Optimization by global ow analysis Global ow =-=[17]-=-, which borrows from similar techniques used in language compilers, attempts to reduce the number of connections in a network by analyzing the relationships between nets on a global basis. For example... |

2 |
Ginneken, “Fanin Ordering in Multi-Slot Timing Analysis
- van
- 1992
(Show Context)
Citation Context ...ormulated as a bipartite matching problem, and optimal ordering can be found in O[n 2p n ln(n)] time, where n is the number of commutative pins. The fanin ordering 27salgorithm employed in BooleDozer =-=[24]-=- gives optimal results over a wide range of delay models. A simple example of fanin ordering is shown in Figure 17. In this example if signal B is critical and signal C is not they can be switched so ... |

2 |
Complete Mapping Library for Lookup-Table-Based FPGAs,” presented at
- Trimberger, Small
- 1992
(Show Context)
Citation Context ...le k-input functions (22k) is prohibitively large for k greater than 3. The size of the library can be signi cantly reduced by using equivalent classes based on symmetries and input/output inversions =-=[28, 29]-=-. For example, the library size for 4-input LUTs can be reduced from 65 536 to 223 functions. The results for the BooleDozer library-based technology mapper using these reduced libraries are better on... |

2 |
Implementation of the PowerPC 601 Microprocessor
- Brodnax, Billings, et al.
- 1994
(Show Context)
Citation Context ...er has been used within IBM to design many high-performance microprocessors and ASIC chips. A short description of some representative designs is given below. The control logic for the PowerPC 601 TM =-=[44]-=-, PowerPC 603 TM , and PowerPC 604 TM was designed in a proprietary high-level language, DSL, and synthesized using BooleDozer. 40sA high-performance PowerPC TM chip set optimized for commercial opera... |

1 |
BDDMAP: A technology mapper based on anewcovering algorithm
- Kung, Damiano, et al.
(Show Context)
Citation Context ...or-one for vectored statements). BooleDozer has more freedom with DATA FLOW logic. Rather than mapping this logic directly 19sinto the technology, the structure is used to \seed" the mapping patterns =-=[15]-=- providing what is known to be a good structure, while allowing the pattern matching functions to nd other viable matches. Any DIRECT logic for which no direct technology map exists is treated like DA... |

1 |
Method for identifying technology primitives in logic functions
- Trevillyan, Damiano, et al.
- 1992
(Show Context)
Citation Context ...ER, MUX, and DECODER. are obtained using rule-based and direct matching tech23sniques. Decomposition matches are obtained mainly by a novel functional matching technique known as truth-table matching =-=[23]-=-. The Boolean functions of the subnetwork and the technology gates are represented by truth tables which are a more convenient representation than BDD's for the functional decomposition problem. Match... |

1 |
An experiment in technology mapping for FPGAs using a xed library
- Trevillyan
- 1993
(Show Context)
Citation Context ...le k-input functions (22k) is prohibitively large for k greater than 3. The size of the library can be signi cantly reduced by using equivalent classes based on symmetries and input/output inversions =-=[28, 29]-=-. For example, the library size for 4-input LUTs can be reduced from 65 536 to 223 functions. The results for the BooleDozer library-based technology mapper using these reduced libraries are better on... |

1 |
A multi-chip device partitioning process
- Kung, Reddy
- 1994
(Show Context)
Citation Context ... to partition a design. The underlying algorithm of the partitioner is based on a linear time graph partitioning heuristic [30]. The BooleDozer partitioner uses a novel multistep partitioning process =-=[31]-=- which is geared toward minimizing both the number of the segments and the total number of I/O pins in the resulting partition. The following is a brief overview of the partitioning process. A FPGA ha... |

1 |
P.P.van Ginneken, \E cient orthonormality testing for synthesis with pass-transistor selectors
- Berkelaar, P
- 1995
(Show Context)
Citation Context ...es nd an input pattern), the implication is false; if the test generator can prove that there is no such input pattern, the implication is true. Justi cation questions are used in selector generation =-=[38]-=-, false path analysis [39, 40], and other synthesis tasks. Before using the test generator, BooleDozer performs good-machine simulation of the whole design. The number of patterns is a parameter, whic... |