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...are significant and account for an average of over 40% of all operations executed. The incidence of integer arithmetic operations in network processing workloads are 26% higher than that in SPECint92 =-=[15]-=- and is lower than that of media processing applications [2] by about 10%. In order to identify operations that account for the large fraction of integer arithmetic operations, we plot the breakup of ...

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...load Our workload is characteristic of applications involved in network processing and are drawn from the following benchmarks available in the public domain: Commbench [10], Netbench [9] and MiBench =-=[8]-=-. Table 2 describes the applications used in this study along with their inputs (provided with the benchmark). The mix of applications chosen for this study are intended to be representative of the pr...

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...of-order superscalar processors require extensive hardware support to eliminate false dependencies [18] and to maintain precise exceptions [19, 20] which do not scale well with increasing issue width =-=[1]-=-. The hardware complexity associated with dynamic scheduling affects clock speed, increases energy consumption and adversely affects development time and costs. In-order superscalar architectures only...

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... help in the design and development of statically scheduled network processors. In this context we evaluate the performance of aggressive compiler techniques such as the superblock [5] and hyperblock =-=[6]-=- optimizations that exploit microarchitectural support for speculation and predication [7] respectively. We explore these optimizations in the context of two processor architectures: in-order supersca...

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...nce data that could help in the design and development of statically scheduled network processors. In this context we evaluate the performance of aggressive compiler techniques such as the superblock =-=[5]-=- and hyperblock [6] optimizations that exploit microarchitectural support for speculation and predication [7] respectively. We explore these optimizations in the context of two processor architectures...

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...tform for the design and development of application specific processors (ASP) [4]. Previous architectural evaluations for network processing have focused mainly on dynamically scheduled architectures =-=[11, 10, 9]-=-. While the benefits of static scheduling for application specific network processors are apparent, there is no literature that reports performance data for this class of processors. This paper aims t...

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...tform for the design and development of application specific processors (ASP) [4]. Previous architectural evaluations for network processing have focused mainly on dynamically scheduled architectures =-=[11, 10, 9]-=-. While the benefits of static scheduling for application specific network processors are apparent, there is no literature that reports performance data for this class of processors. This paper aims t...

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...duled superscalar processors use out-of-order execution. Out-of-order superscalar processors require extensive hardware support to eliminate false dependencies [18] and to maintain precise exceptions =-=[19, 20]-=- which do not scale well with increasing issue width [1]. The hardware complexity associated with dynamic scheduling affects clock speed, increases energy consumption and adversely affects development...

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...g technology demands higher performance and increased flexibility from the processing element in the networking hardware. This has lead to the introduction of several network processors in the market =-=[13]-=-. Future network processor designs will be expected to deliver higher performance with low energy consumption and minimal costs while being flexible enough to support complex protocols, all within a s...

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...duled superscalar processors use out-of-order execution. Out-of-order superscalar processors require extensive hardware support to eliminate false dependencies [18] and to maintain precise exceptions =-=[19, 20]-=- which do not scale well with increasing issue width [1]. The hardware complexity associated with dynamic scheduling affects clock speed, increases energy consumption and adversely affects development...

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... operations executed. The incidence of integer arithmetic operations in network processing workloads are 26% higher than that in SPECint92 [15] and is lower than that of media processing applications =-=[2]-=- by about 10%. In order to identify operations that account for the large fraction of integer arithmetic operations, we plot the breakup of integer arithmetic operation frequencies as shown in Figure ...

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...ity from the hardware onto the 1 Very Long Instruction Wordscompiler, making statically scheduled processors a popular platform for the design and development of application specific processors (ASP) =-=[4]-=-. Previous architectural evaluations for network processing have focused mainly on dynamically scheduled architectures [11, 10, 9]. While the benefits of static scheduling for application specific net...

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...significant role in the maximum performance that can be derived from increasing processor clock frequency. These results suggest opportunities for efficient latency hiding techniques (eg. prefetching =-=[17]-=-) to improve performance with increased clock frequencies. 6. CONCLUSIONS AND FUTURE WORK This paper presents the results obtained from a study of static scheduling for networking applications. We sum...

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...tform for the design and development of application specific processors (ASP) [4]. Previous architectural evaluations for network processing have focused mainly on dynamically scheduled architectures =-=[11, 10, 9]-=-. While the benefits of static scheduling for application specific network processors are apparent, there is no literature that reports performance data for this class of processors. This paper aims t...

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...nds on the speculation model assumed and the processor support for speculation. As processor support for speculation leads to complex hardware implementations, we assume the general speculation model =-=[12]-=- in our experiments. The general speculation model enforces lesser restrictions on the instructions that can be speculated without significantly increasing the hardware support required. In this model...

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... execute in-order while dynamically scheduled superscalar processors use out-of-order execution. Out-of-order superscalar processors require extensive hardware support to eliminate false dependencies =-=[18]-=- and to maintain precise exceptions [19, 20] which do not scale well with increasing issue width [1]. The hardware complexity associated with dynamic scheduling affects clock speed, increases energy c...

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...ntext we evaluate the performance of aggressive compiler techniques such as the superblock [5] and hyperblock [6] optimizations that exploit microarchitectural support for speculation and predication =-=[7]-=- respectively. We explore these optimizations in the context of two processor architectures: in-order superscalar and VLIW, with varying degrees of support for these optimizations. As we expect future...