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...3D-MPSoCs. The EDP and temperature profile are calculated for 2-tier and 4-tier configuration for the multi-threaded PARSEC benchmarks. 42 4.2.5 PARSEC Benchmarks The multi-threaded PARSEC benchmarks =-=[4]-=- was jointly developed by Intel and Princeton university. The PARSEC benchmarks are developed from real-time application such as computer vision, engineering, animation etc. The PARSEC benchmarks are ...

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...rser NVM PowersTracer NVSim Stats.txt Config.ini Power.xml Figure 4.7: Design-flow of Run time simulation framework used for the investigation of emerging NVMs in 3D-MPSoCs PAT power simulator. McPAT =-=[39]-=- models dynamic power, sub-threshold leakage and gate leakage power for 3D-MPSoC architecture. NVM power tracer calculates the NVM L2 cache power using the power values obtained from McPAT and NVSim. ...

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... to simulate the power, performance and thermal profiles of 3D-MPSoCs. The general flow of 39 run-time thermal and performance simulation framework developed in this work is shown in Figure 4.7. Gem5 =-=[5]-=- is used an architectural simulation platform for the proposed 3DMPSoC architecture. The architectural configuration and cache access latencies used in the simulation are shown in Table 4.5. The cache...

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...ng the high heat dissipation in 3D-ICs [57]. Design-time thermal management aims at achieving a thermal-aware 3D-IC floorplan design using methods such as floorplanning, TSV and thermal-via placement =-=[16, 17]-=-. Run-time thermal management involves continuous monitoring and controlling of the temperature during the run-time. Methods such as task scheduling, task migration and dynamic voltage frequency scali...

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...tion space. SA algorithm uses annealing process of metals, which assume low energy equilibrium when slowly cooled from high temperatures [55]. The pseudo code for SA algorithm is shown in Algorithm 1 =-=[2]-=-. SA algorithm consist of current (S), temporary (Stemp) and best (Sbest) solutions. The current solution is updated at each iteration using random assignment. The temporary solution is updated when i...

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...rative process to optimize a combinational problem and improve the solution through successive iterations. In practice, the combinational problems such as arrangement, grouping, ordering or selection =-=[51]-=- have a very large solution space. An exhaustive search to find the most optimal solution to these problems requires extremely large amount of time and is sometimes infeasible [55]. Hence, these meta-...

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...ng the high heat dissipation in 3D-ICs [57]. Design-time thermal management aims at achieving a thermal-aware 3D-IC floorplan design using methods such as floorplanning, TSV and thermal-via placement =-=[16, 17]-=-. Run-time thermal management involves continuous monitoring and controlling of the temperature during the run-time. Methods such as task scheduling, task migration and dynamic voltage frequency scali...

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.... HPD is the highest power density. It denotes the highest power grid in the grid matrix, that contributes to the maximum temperature of the 3D-IC stack. 25 3.5 Interconnect Length (Lwire) Prior work =-=[29, 16, 43, 11]-=- in TSV placement used half perimeter wire length (HPWL), to calculate the interconnect length in 3D-ICs. The interconnect length calculation using HPWL is shown in Figure 3.3(a). HPWL is sum of half-...

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...ngth between the functional units. In addition, 3D-ICs supports heterogeneous integration of different technologies such as emerging non-volatile memories (NVMs), RF, MEMS, analog and optical systems =-=[64]-=- in a single chip. 3D-ICs have high package density and small form factor with reduced footprint and weight [67]. Moreover, 3D-ICs reduce the cost for large designs (more than 100M gates) compared to ...

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...ave high package density and small form factor with reduced footprint and weight [67]. Moreover, 3D-ICs reduce the cost for large designs (more than 100M gates) compared to planar integrated circuits =-=[24]-=-. For large designs, the reduction in the cost of metal layers overcomes the cost due to increased die area of 3D-ICs. Despite these advantages, one of the major problem in 3D-ICs is the high chip tem...

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...power and MLC storage. For instance, a 2-bit/cell STTRAM operation using MgO-based MJT was demonstrated by Seagate technology [46]. Furthermore, STTRAM has fast access time compared to RRAM and PCRAM =-=[23]-=-. Hitachi and Tohoku university jointly demonstrated a 1.8 V 0.2 µm 2 Mb STTRAM using MgO tunneling barrier and demonstrated a cell efficiency of 40% [31]. Moreover, STTRAM has a good thermal performa...

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...ation of 3-tier 3D-IC used in TSV placement . . . . . . . . . 32 4.4 Generic 1T1R Architecture Representation . . . . . . . . . . . . . . . . . . 36 4.5 Generic NVM L2 Cache Organization adapted from =-=[25]-=- . . . . . . . . . . 37 4.6 PCRAM SET and RESET operation adapted from [25] . . . . . . . . . . . 38 4.7 Design-flow of Run time simulation framework used for the investigation of emerging NVMs in 3D-...

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...f the thermal vias depends on the implementation and maximum temperature of the 3D-ICs. It is estimated that thermal vias consume 10% - 20% of the chip area for a maximum temperature reduction of 47% =-=[28, 44]-=-. On the other hand, based on 5Microbumps Dielectricsoxide M1 M2 M3 Devices TSV Tier 3 Tier 2 Tier 1 Substrate Bonding layer M1 M2 M3 M2 M3 M1 Substrate Substrate Bonding layer Figure 1.2: A 3-tier 3D...

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...ment and 15 adjustment between the macro-blocks. The peak temperature of 3D-IC is reduced to 85◦ C with 80% lesser thermal vias and a trade off of 2% increase in the interconnect length. Goplen et al =-=[27]-=- proposed an multi-level analytical and partition based TSV placement MCNC and GSRCsbenchmarks TSV numbersestimation Distribution andsAdjustment InitialsPlacement TSV distribution TSV Assignment TSV A...

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...n 3D-ICs offers integration of novel technologies such as emerging NVMs in a single chip. Emerging memory technologies such as RRAM, PCRAM and STTRAM are being actively researched in the recent times =-=[70, 59, 6]-=-. Compared to the 10 SRAM, these emerging technologies are non-volatile, requiring a little/zero power to maintain the stored state. Due to the reduced static power consumption, these NVMs can be used...

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... The general flow of design-time TSV placement framework is shown in Figure 4.1. The framework (developed in C++) integrates a customized floorplanning tool (3DFP) [29] and thermal simulator (3D-ICE) =-=[60]-=-. The framework uses macro-blocks, TSV definition, netlist and design information to generate an optimized TSV placed floorplan for 3D-ICs. The initial placement of macro-blocks is achieved in 3DFP by...

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...the cells to avoid undesirable heating (thermal cross talk) from the neighbouring cells. While, STTRAM requires a high current to change the direction of the magnetic layer during the write operation =-=[72]-=-. On the other hand, RRAM consumes a very low dynamic energy compared to the PCRAM and STTRAM [50]. Despite the above challenges, the advantages such as low static power, relatively high thermal perfo...

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.... HPD is the highest power density. It denotes the highest power grid in the grid matrix, that contributes to the maximum temperature of the 3D-IC stack. 25 3.5 Interconnect Length (Lwire) Prior work =-=[29, 16, 43, 11]-=- in TSV placement used half perimeter wire length (HPWL), to calculate the interconnect length in 3D-ICs. The interconnect length calculation using HPWL is shown in Figure 3.3(a). HPWL is sum of half-...

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...hodology used for the investigation of different NVMs are also discussed in this section. 4.2.1 Characteristics of NVMs Table 1 summarizes the characteristics of NVMs based on the data collected from =-=[69, 21, 45, 25, 48, 46, 14, 12]-=-. RRAM provides high storage capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was ...

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...cts placed between the tiers in 3D-ICs. A 3-tier 3D-IC where inter-tier networks are connected using TSVs is shown in Figure 1.2. Polysilicon, copper and tungsten are most commonly used TSV materials =-=[56]-=-. As shown in Figure 1.2, dielectric oxide is used for the isolation between TSV and silicon substrate. The micro-bumps are used to connect TSVs in the bonding layer between the tiers. Based on the pu...

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...application of heat by the heater. MOSFET access device is shown in Figure 1.5. The phase change material used is a chalcogenide glass (Ge2Sb2Te2) which is alloys of germanium, antimony and tellurium =-=[30]-=-. The crystalline phase and amorphous phase shows low resistivity and high resistivity respectively. A heater is placed below the PCM for applying the heat for switching. The crystalline state is achi...

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...s fast access time compared to RRAM and PCRAM [23]. Hitachi and Tohoku university jointly demonstrated a 1.8 V 0.2 µm 2 Mb STTRAM using MgO tunneling barrier and demonstrated a cell efficiency of 40% =-=[31]-=-. Moreover, STTRAM has a good thermal performance among the NVMs. For instance, STTRAM withstanding a temperature of 150◦ C with 10 years of data retention was demonstrated by Ono et al. [50]. However...

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...ve metal oxide technology [10, 13]. Furthermore, RRAM has the ability to withstand a very high temperature. For instance, RRAM withstanding the temperature up to 200◦ C was demonstrated by Lee et al. =-=[36]-=-. They achieved an endurance of greater than 106 cycles and 10 years of data retention at 200◦ C. However, RRAM has the problem of limited endurance (105-1010 cycles). 34 PCRAM has low static power an...

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...hodology used for the investigation of different NVMs are also discussed in this section. 4.2.1 Characteristics of NVMs Table 1 summarizes the characteristics of NVMs based on the data collected from =-=[69, 21, 45, 25, 48, 46, 14, 12]-=-. RRAM provides high storage capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was ...

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...in this work. 19 Chapter 3 Weight-Based Simulated Annealing (WSA) WSA algorithm uses a weight constraint for the placement of TSVs in 3D-ICs. Simulated annealing (SA) algorithm used in previous works =-=[16, 41]-=- contains randomness in the placement of TSVs. WSA algorithm replaces the randomness in SA algorithm by a weight constraint, to reduce the free space created on inserting TSVs in the floorplan. WSA al...

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...e switching achieved by passing high current in the free layer. . . . . . . . . . . . . . . . . . . . . . 11 2.1 Design-flow of TSV placement used to reduce the peak temperature in 3DICs adapted from =-=[18]-=- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Flowchart of Weight Simulated Annealing (WSA) used for the TSV placement in 3D-ICs . . . . . . . . . . . . . . . . . . . . . . . . . ....

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...of 3D-ICs. For instance, the thermal conductivity of epoxy used as dielectric between the tiers is very low (1.7 W/mK) compared to the thermal conductivity of copper (400 W/mK) and silicon (150 W/mK) =-=[73]-=-. The overall power density of a 3D-IC stack will be √ N times the 3power density of corresponding 2D die (where N is the number of stacks and the dies are assumed to be homogeneous with equal power d...

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...and Yj . WSA verifies the overlap between the via groups, after satisfying the weight constraint. Via groups vl and vm overlap each other, if at least one of the following conditions is not satisfied =-=[40]-=- xl + wl ≤ xm xl ≥ xm + wm yl + hl ≤ ym yl ≥ ym + hm (3.3) 23 where, wl, wm and hl, hm represents the width and height of the via groups vl and vm respectively. The via groups are enclosed within the ...

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...ate Liquid-flow tier 2 tier 3 Figure 4.3: Stack configuration of 3-tier 3D-IC used in TSV placement 4.1.3 MCNC’91 and GSRC Benchmarks Microelectronics center for North Carolina (MCNC) benchmark suite =-=[35]-=- were published at theMCNC’91 workshop on the logical synthesis. MCNC’91 benchmarks (ami33, ami49, hp and xerox) are collected from the industry which ranges from simple circuit to advanced circuit. G...

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...The pitch of the TSVs ranges from 10 µm to 200 µm [65] in via-first to via-last technologies 6respectively. Furthermore, the cost of fabrication of these TSVs are very high using current technologies =-=[42]-=-. Hence, the placement of the TSVs are extremely important in reducing the temperature of 3D-ICs. Meta-heuristic algorithms offer good floorplanning solutions for the placement of TSVs. 1.2.2 Meta-Heu...

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...f the thermal vias depends on the implementation and maximum temperature of the 3D-ICs. It is estimated that thermal vias consume 10% - 20% of the chip area for a maximum temperature reduction of 47% =-=[28, 44]-=-. On the other hand, based on 5Microbumps Dielectricsoxide M1 M2 M3 Devices TSV Tier 3 Tier 2 Tier 1 Substrate Bonding layer M1 M2 M3 M2 M3 M1 Substrate Substrate Bonding layer Figure 1.2: A 3-tier 3D...

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...e designs, the reduction in the cost of metal layers overcomes the cost due to increased die area of 3D-ICs. Despite these advantages, one of the major problem in 3D-ICs is the high chip temperatures =-=[54]-=-, due to increased power density (∼ 250 W/cm2) per unit surface area of the stack. The high power density is caused by vertical stacking of active devices and poor thermal conductivity of the bonding ...

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...hodology used for the investigation of different NVMs are also discussed in this section. 4.2.1 Characteristics of NVMs Table 1 summarizes the characteristics of NVMs based on the data collected from =-=[69, 21, 45, 25, 48, 46, 14, 12]-=-. RRAM provides high storage capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was ...

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...hodology used for the investigation of different NVMs are also discussed in this section. 4.2.1 Characteristics of NVMs Table 1 summarizes the characteristics of NVMs based on the data collected from =-=[69, 21, 45, 25, 48, 46, 14, 12]-=-. RRAM provides high storage capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was ...

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...erall power density of a 3D-IC stack will be √ N times the 3power density of corresponding 2D die (where N is the number of stacks and the dies are assumed to be homogeneous with equal power density) =-=[32]-=-. The power density can be further exacerbated with heterogeneous integration. The high temperature effects the performance, power, reliability and life span of 3D-ICs [19]. At high temperature, the s...

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...IC implemented using micro-channels, a pump and a heat exchanger coolant. By managing the above three parameters the heat flux as high as 3.9 kW/cm3 can be extracted from the tiers of the 3D-IC stack =-=[53]-=-. However, sufficient amount of energy is spent in the fluid pump and heat exchanger for controlling the pressure and temperature of the coolant respectively. Hence, the liquid cooling mechanism is us...

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...have been considered to alleviate heat generated in the 3D-IC stack. Cooling mechanisms such as conventional heat sink and micro-channel cold plates are inadequate to dissipate large heat from 3D-ICs =-=[61]-=-. While TSVs are limited in number due to their cost of fabrication and large area, inter-tier liquid cooling is an efficient cooling mechanism capable of removing high heat dissipated in a 3D-IC stac...

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... the oxide region. Several metal oxides are used for the fabrication of RRAM such as hafnium oxide (HfOx), titanium oxide (TiOx), copper oxide (CuOx), aluminium oxide (AlOx), nickel oxide (NiOx) etc. =-=[68]-=-. PCRAM switches between crystalline and amorphous state in phase change material (PCM) on the application of heat. The schematic of phase change material used with 11 WL SL BL n+ n+ P substrate Top e...

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... bonding of dies. The size of the TSVs varies between the via-first and via-last technology, due to the aspect ratio requirement corresponding to the thickness of the wafer used in these technologies =-=[71]-=-. For instance, the dimension of the TSVs range from 1 µm to 90 µm in via-first to via-last technologies respectively [71]. These TSVs occupy a large area between the functional units in 3D-ICs. For i...

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...A algorithm has smaller simulation time and uses less computational resources compared to other general optimization methods [1]. In addition, SA algorithm is capable of scaling with the problem size =-=[7]-=-. However, the SA algorithm heuristic has to be tuned for fast and efficient convergence to the global optimum [26]. The TSV placement is a large solution space problem in which the meta-heuristic alg...

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...nation of different sized components such as heaters for PCRAM [10]. Unity semiconductor demonstrated the largest test array of 0.13 µm 64 MB multilayered RRAM using conductive metal oxide technology =-=[10, 13]-=-. Furthermore, RRAM has the ability to withstand a very high temperature. For instance, RRAM withstanding the temperature up to 200◦ C was demonstrated by Lee et al. [36]. They achieved an endurance o...

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... metal interconnects increases with temperature. The leakage power of 3D-ICs also varies linearly with temperature. For instance, every 30 K increase in temperature increases the leakage power by 30% =-=[62]-=-. Moreover, the reliability of 3D-ICs exponentially depends on temperature. For example, the mean time to failure is reduced by a factor of 10 with every 30 K rise in temperature [63]. It is also esti...

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.... HPD is the highest power density. It denotes the highest power grid in the grid matrix, that contributes to the maximum temperature of the 3D-IC stack. 25 3.5 Interconnect Length (Lwire) Prior work =-=[29, 16, 43, 11]-=- in TSV placement used half perimeter wire length (HPWL), to calculate the interconnect length in 3D-ICs. The interconnect length calculation using HPWL is shown in Figure 3.3(a). HPWL is sum of half-...

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...hodology used for the investigation of different NVMs are also discussed in this section. 4.2.1 Characteristics of NVMs Table 1 summarizes the characteristics of NVMs based on the data collected from =-=[69, 21, 45, 25, 48, 46, 14, 12]-=-. RRAM provides high storage capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was ...

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...power TSVs, while TSVs used for inter-tier networks are called signal TSVs. The size of power TSVs are larger than the signal TSVs to reduce the voltage drop and meet the current density requirements =-=[33]-=-. For instance, Lee et al. [37] used the 40 µm and 10 µm size for the power and signal TSVs in a 45 nm technology. In addition, TSVs used specifically for the heat dissipation are called thermal vias....

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... placement of TSVs. In addition, they reduced the peak temperature of 3D-IC to 85◦ C using micro-channel liquid cooling with coolant temperature of 20◦ C and 70 kPa pressure drop. 17 Later, Lee et al =-=[38]-=- focused on the reliability analysis and optimization of various design parameters of TSVs with inter-tier liquid cooling. On the other hand, Sridhar et al [61] have proposed a flexible compact transi...

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...hodology used for the investigation of different NVMs are also discussed in this section. 4.2.1 Characteristics of NVMs Table 1 summarizes the characteristics of NVMs based on the data collected from =-=[69, 21, 45, 25, 48, 46, 14, 12]-=-. RRAM provides high storage capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was ...

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...uring write operation, a positive voltage is applied on the BL to store high resistance state in RRAM cell. While, a negative voltage is applied on the BL to store a low resistance state in RRAM cell =-=[47]-=-. Read and Write Operation of PCRAM PCRAM represent logic ’1’ and logic ’0’ as crystalline and amorphous states respectively in PCM [8]. Read operation involves application of a small positive voltage...

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...e, thermal management plays a pivotal role in controlling the temperature of 3D-ICs. Design-time and run-time thermal management techniques are used for mitigating the high heat dissipation in 3D-ICs =-=[57]-=-. Design-time thermal management aims at achieving a thermal-aware 3D-IC floorplan design using methods such as floorplanning, TSV and thermal-via placement [16, 17]. Run-time thermal management invol...

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...f thermal expansion between TSVs and the silicon substrate. Hence, TSVs require a minimum distance (pitch size) from other TSVs and functional units. The pitch of the TSVs ranges from 10 µm to 200 µm =-=[65]-=- in via-first to via-last technologies 6respectively. Furthermore, the cost of fabrication of these TSVs are very high using current technologies [42]. Hence, the placement of the TSVs are extremely i...

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...ies such as emerging non-volatile memories (NVMs), RF, MEMS, analog and optical systems [64] in a single chip. 3D-ICs have high package density and small form factor with reduced footprint and weight =-=[67]-=-. Moreover, 3D-ICs reduce the cost for large designs (more than 100M gates) compared to planar integrated circuits [24]. For large designs, the reduction in the cost of metal layers overcomes the cost...

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...n 3D-ICs offers integration of novel technologies such as emerging NVMs in a single chip. Emerging memory technologies such as RRAM, PCRAM and STTRAM are being actively researched in the recent times =-=[70, 59, 6]-=-. Compared to the 10 SRAM, these emerging technologies are non-volatile, requiring a little/zero power to maintain the stored state. Due to the reduced static power consumption, these NVMs can be used...

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...e best solution gives the optimized result of the combinational problem. 7SA algorithm has smaller simulation time and uses less computational resources compared to other general optimization methods =-=[1]-=-. In addition, SA algorithm is capable of scaling with the problem size [7]. However, the SA algorithm heuristic has to be tuned for fast and efficient convergence to the global optimum [26]. The TSV ...

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....6. [25] Figure 4.6: PCRAM SET and RESET operation adapted from [25] Read and Write Operations of STTRAM STTRAM uses parallel and anti-parallel state to represent logic ’0’ and logic ’1’ respectively =-=[3]-=-. Read operation involves the application of very small negative voltage across the BL and source line (SL) line. The value of current through the MJT is determined by its resistance. A current sense ...

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...n 3D-ICs offers integration of novel technologies such as emerging NVMs in a single chip. Emerging memory technologies such as RRAM, PCRAM and STTRAM are being actively researched in the recent times =-=[70, 59, 6]-=-. Compared to the 10 SRAM, these emerging technologies are non-volatile, requiring a little/zero power to maintain the stored state. Due to the reduced static power consumption, these NVMs can be used...

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... applied on the BL to store a low resistance state in RRAM cell [47]. Read and Write Operation of PCRAM PCRAM represent logic ’1’ and logic ’0’ as crystalline and amorphous states respectively in PCM =-=[8]-=-. Read operation involves application of a small positive voltage on the BL and a current sense amplifier is used to sense the data in PCRAM cell. The PCM is heated by passing the electric current to ...

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...AM has low leakage power, the dynamic power consumption is high in these NVMs. PCRAM consumes a high dynamic energy due to the high current required to switch between crystalline and amorphous states =-=[9]-=-. In addition to high dynamic energy, PCRAM also requires a minimum distance between the cells to avoid undesirable heating (thermal cross talk) from the neighbouring cells. While, STTRAM requires a h...

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...n addition, RRAM has a simple metal-insulator-metal structure for fabrication compared to multiple magnetic structure in STTRAM and combination of different sized components such as heaters for PCRAM =-=[10]-=-. Unity semiconductor demonstrated the largest test array of 0.13 µm 64 MB multilayered RRAM using conductive metal oxide technology [10, 13]. Furthermore, RRAM has the ability to withstand a very hig...

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...hodology used for the investigation of different NVMs are also discussed in this section. 4.2.1 Characteristics of NVMs Table 1 summarizes the characteristics of NVMs based on the data collected from =-=[69, 21, 45, 25, 48, 46, 14, 12]-=-. RRAM provides high storage capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was ...

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...ge capacity due to smaller cell size. In addition, RRAM offers low operating voltage and multi-level cell (MLC) storage. A 40 nm 3-bit/cell and 2-bit/cell RRAM operation was demonstrated by Macronics =-=[15]-=-. They achieved a endurance of 103 with operating voltage of 0.4 V . In addition, RRAM has a simple metal-insulator-metal structure for fabrication compared to multiple magnetic structure in STTRAM an...

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...s with equal power density) [32]. The power density can be further exacerbated with heterogeneous integration. The high temperature effects the performance, power, reliability and life span of 3D-ICs =-=[19]-=-. At high temperature, the speed of the transistors is reduced due to the degradation in mobility of the carriers. The performance of clock buffers degrades ( 1.2%-1.32% for every 10K increase [64]) a...

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... given as inputs to the 3D-ICE for thermal analysis. 3D-ICE uses compact transient thermal model (CTTM) to simulate the thermal profile of 3D-ICs and solve the resulting equation matrix using SuperLU =-=[20]-=-, a 30 Table 4.1: Floorplan and Thermal analysis parameters used in the simulation of 3D-ICs Parameter Value TSV size 20µm X 20 µm Number of layers 3 silicon thickness 50µm layer thickness 2µm pin-fin...

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...e operations of each NVMs. 37 Figure 4.5: Generic NVM L2 Cache Organization adapted from [25] Read and Write Operation of RRAM RRAM 1T1R cell store logic ’0’ and logic ’1’ in LRS and HRS respectively =-=[22]-=-. During the read operation, a small voltage is applied on the bit line (BL) of the 1T1R RRAM cell. The read voltage is maintained typically small, to ensure the read operation does not disturb the va...

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...ologies respectively [71]. These TSVs occupy a large area between the functional units in 3D-ICs. For instance, 90000 signal TSVs of 5 µm dimension occupy an area equal to one million gates of 1.5 µm =-=[34]-=-. In addition, TSVs induce stress in the surrounding regions due to the difference in the co-efficient of thermal expansion between TSVs and the silicon substrate. Hence, TSVs require a minimum distan...

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... inter-tier networks are called signal TSVs. The size of power TSVs are larger than the signal TSVs to reduce the voltage drop and meet the current density requirements [33]. For instance, Lee et al. =-=[37]-=- used the 40 µm and 10 µm size for the power and signal TSVs in a 45 nm technology. In addition, TSVs used specifically for the heat dissipation are called thermal vias. The size of the thermal vias d...

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...ycles and 32 kB page of 2-bit/cell for 109 read cycles. In addition, Samsung has demonstrated a 512 MB PCRAM array with a write endurance of 105 cycles with a data retention time of 10 years at 85◦ C =-=[49]-=-. The thermal performance of PCRAM is limited by its crystallization temperature, as switching is achieved through heating the PCM [10]. For instance, Pellizer et al. [52] demonstrated the thermal per...

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...y of 40% [31]. Moreover, STTRAM has a good thermal performance among the NVMs. For instance, STTRAM withstanding a temperature of 150◦ C with 10 years of data retention was demonstrated by Ono et al. =-=[50]-=-. However, STTRAM has a large cell size which leads to lower storage capacity compared to RRAM and PCRAM. 35 Although, PCRAM and STTRAM has low leakage power, the dynamic power consumption is high in ...

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...on time of 10 years at 85◦ C [49]. The thermal performance of PCRAM is limited by its crystallization temperature, as switching is achieved through heating the PCM [10]. For instance, Pellizer et al. =-=[52]-=- demonstrated the thermal performance of 110◦ C with 10 years of data retention time. STTRAM has relatively very high endurance of greater than 1016 cycles, compared to RRAM and PCRAM. In addition, ST...

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...dering or selection [51] have a very large solution space. An exhaustive search to find the most optimal solution to these problems requires extremely large amount of time and is sometimes infeasible =-=[55]-=-. Hence, these meta-heuristic algorithms use randomness in the search process to find the optimal or near optimal solution for the combinational problems. Meta-heuristic algorithms are not problem spe...

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...cooling is an efficient cooling mechanism capable of removing high heat dissipated in a 3D-IC stack [61]. A generic schematic of a liquid cooling system used for a 2-tier 3D-IC is shown in Figure 1.3 =-=[58]-=-. The heat sinks are embedded between the tiers of the 3D-IC stack. The fluid coolant moves through the heat sink and absorbs the heat from the tiers. The liquid cooling system needs one or more fluid...

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...age power by 30% [62]. Moreover, the reliability of 3D-ICs exponentially depends on temperature. For example, the mean time to failure is reduced by a factor of 10 with every 30 K rise in temperature =-=[63]-=-. It is also estimated that 10%-15% increase of temperature causes 50% reduction in the life span of the device. Furthermore, hotspots can permanently damage the 3D-ICs. Therefore, thermal management ...

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...ent of the 3D-IC stack. Semiconductor companies such as HP, Toshiba and Samsung are exploring the possibility of replacing conventional SRAM on-chip memory with these emerging NVMs in the near future =-=[66]-=-. Different NVMs use different mechanisms to store the data. RRAM uses resistive W Top electrode Bottom electrode Low oxygensvacancysconcentration High oxygensvacancysconcentration Figure 1.4: A metal...