#### DMCA

## LOW POWER DCT USING HIGHLY SCALABLE MULTIPLIERS

### Citations

509 |
Discrete Cosine Transform: Algorithms, Advantages, Applications
- RAO, YIP
- 1990
(Show Context)
Citation Context ...y.sDCT is a complex operation and uses significant amount ofscomputing resources. Thus fast transforms such as the fastsdiscrete cosine transform (DCT) are often used to meetsrealtime constraints [1],=-=[2]-=-,[5].sDue to the use of multipliers, a significant amount of powersand computations are required in image and video codingsfor direct and inverse transform operations (DCT/IDCT). Asmultiplication is c... |

9 | A simple processor core design for DCT/IDCT
- Chang, Kung, et al.
- 2000
(Show Context)
Citation Context ... single pass in thesbutterfly diagram and it is represented with one of the 4sdifferent sparse matrices. Fast DCT implementationsspartition the 8x8 transform matrix into four different stagess[3],[4],=-=[6]-=-. The transform matrix can then be expressed assthe product of 4 sparse matrices:s[T]8x8 = [T4]8x8[T3]8x8[T2]8x8[T1]8x8s(7)sEach single pass results in intermediate values of varyingsmagnitude.sThe ma... |

8 |
Image quality assesment: from error visibility to structural similarity,”
- Wang, Bovik, et al.
- 2004
(Show Context)
Citation Context ... by its corresponding ATC average power for FSM using 8, 16 shows the average power for SVM a The original input image is compar after the whole process (D Quantization-IDCT) to evaluate the and SSIM =-=[7]-=- algorithms. The perfo fixed size, fixed-size per block, and is summarized in Tables 7-9. T significant amount of power has bee of a multiplier is adjusted per b overhead in reconfiguring the mult res... |

8 | Analysis and Design of Low Power Digital Multipliers”
- Meier
- 1999
(Show Context)
Citation Context ...er with Fixed Size fors• Scalable Multiplier with Variable Size f The power consumption for every case is an three different algorithms for multiplica Scalable Multiplier (HSM) [8], Wallace M [8],[9],=-=[10]-=- and Array Multiplier (AM)[8], consumption in CMOS digital circuits is switching activity in logic gates; the totalsthat switch is used to calculate the approx power consumption.sIn Table 5 we cansTog... |

5 |
Dynamic range analysis for the implementation of fast transform
- Wan, Wang, et al.
- 1995
(Show Context)
Citation Context ...g to one single pass in thesbutterfly diagram and it is represented with one of the 4sdifferent sparse matrices. Fast DCT implementationsspartition the 8x8 transform matrix into four different stagess=-=[3]-=-,[4],[6]. The transform matrix can then be expressed assthe product of 4 sparse matrices:s[T]8x8 = [T4]8x8[T3]8x8[T2]8x8[T1]8x8s(7)sEach single pass results in intermediate values of varyingsmagnitude... |

3 |
Power comparison of flow-graph and distributed arithmetic based DCT architectures
- Kuhlmann, Parhi
- 1998
(Show Context)
Citation Context ...iency.sDCT is a complex operation and uses significant amount ofscomputing resources. Thus fast transforms such as the fastsdiscrete cosine transform (DCT) are often used to meetsrealtime constraints =-=[1]-=-,[2],[5].sDue to the use of multipliers, a significant amount of powersand computations are required in image and video codingsfor direct and inverse transform operations (DCT/IDCT). Asmultiplication ... |

3 |
A chipset core for image compression
- Artieri, Colavin
- 1990
(Show Context)
Citation Context ... one single pass in thesbutterfly diagram and it is represented with one of the 4sdifferent sparse matrices. Fast DCT implementationsspartition the 8x8 transform matrix into four different stagess[3],=-=[4]-=-,[6]. The transform matrix can then be expressed assthe product of 4 sparse matrices:s[T]8x8 = [T4]8x8[T3]8x8[T2]8x8[T1]8x8s(7)sEach single pass results in intermediate values of varyingsmagnitude.sTh... |

1 |
Low-Power Implementation of Discrete Cosine Transform
- Farag, Elmasry
- 1996
(Show Context)
Citation Context ...CT is a complex operation and uses significant amount ofscomputing resources. Thus fast transforms such as the fastsdiscrete cosine transform (DCT) are often used to meetsrealtime constraints [1],[2],=-=[5]-=-.sDue to the use of multipliers, a significant amount of powersand computations are required in image and video codingsfor direct and inverse transform operations (DCT/IDCT). Asmultiplication is compu... |

1 |
Highly Scalable Multiplier
- Ajmera
- 2003
(Show Context)
Citation Context ...s such assWallace and Array multipliers cannot be scaled dynamicallysand hence a 16 bit multiplier is used even with 8-bitsoperands. A low power multiplier based on operandstruncation was proposed in =-=[8]-=-.sOperand truncation reducessswitching activity and hence reduces power consumption.sThe downside is that truncation leads to quality loss due tosreduce precision. Power consumption can thus be reduce... |

1 |
Low power Multipliers with Data Wordlength Rreduction”. Asilomar conference
- Han, Evans, et al.
(Show Context)
Citation Context ...iplier with Fixed Size fors• Scalable Multiplier with Variable Size f The power consumption for every case is an three different algorithms for multiplica Scalable Multiplier (HSM) [8], Wallace M [8],=-=[9]-=-,[10] and Array Multiplier (AM)[8], consumption in CMOS digital circuits is switching activity in logic gates; the totalsthat switch is used to calculate the approx power consumption.sIn Table 5 we ca... |