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...an be employed to generate data addresses and prefetch well ahead of the main execution, we examine a set of applications drawn from four common benchmark suites (SPEC2000 [16], SPEC95 [10], SPLASH-2 =-=[34]-=-, and Olden [25]). A large number of cache misses in these applications are due to relatively irregular access patterns involving pointers, hash tables, indirect array references, or a mix of them, wh...

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...incur cache misses. Thus, the very first thing is to decide where to launch pre-execution in the program, based on the programmer's knowledge, cache miss profiling [23], or compiler locality analysis =-=[24]-=-. Once this decision has been made, new instructions for spawning pre-execution threads are inserted at the right places in the program. Each threadspawning instruction requests for an idle hardware c...

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...res the computational results of pre-execution. More aggressive schemes that actually use the results of speculative threads have also been proposed. Examples of them are the multiscalar architecture =-=[29]-=-, threadlevel data-speculation (TLDS) [30], threaded multiple path execution (TME) [33], dynamic multithreading (DMT) [2], slipstream processors [31], and speculative data-driven multithreading (DDMT)...

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...licity, our technique offers an average speedup of 24% in a set of irregular applications, which is a 19% speedup over state-of-the-art software-controlled prefetching. 1. Introduction Multithreading =-=[1, 32]-=- and prefetching [8, 20, 22] are two major techniques for tolerating ever-increasing memory latency. Multithreading tolerates latency by executing instructions from another concurrent thread when the ...

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...e-controlled pre-execution can be employed to generate data addresses and prefetch well ahead of the main execution, we examine a set of applications drawn from four common benchmark suites (SPEC2000 =-=[16]-=-, SPEC95 [10], SPLASH-2 [34], and Olden [25]). A large number of cache misses in these applications are due to relatively irregular access patterns involving pointers, hash tables, indirect array refe...

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...fers an average speedup of 24% in a set of irregular applications, which is a 19% speedup over state-of-the-art software-controlled prefetching. 1. Introduction Multithreading [1, 32] and prefetching =-=[8, 20, 22]-=- are two major techniques for tolerating ever-increasing memory latency. Multithreading tolerates latency by executing instructions from another concurrent thread when the running thread encounters a ...

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...e done by the compiler. To facilitate the insertion process, we can have an application programming interface (API) for manipulating preexecution threads. In fact, a similar interface called PThreads =-=[6]-=- has long been used to exploit parallelism using threads. By providing a new API (perhaps we can call it MThreads) or extending the existing PThreads to support pre-execution threads, programmers can ...

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...licity, our technique offers an average speedup of 24% in a set of irregular applications, which is a 19% speedup over state-of-the-art software-controlled prefetching. 1. Introduction Multithreading =-=[1, 32]-=- and prefetching [8, 20, 22] are two major techniques for tolerating ever-increasing memory latency. Multithreading tolerates latency by executing instructions from another concurrent thread when the ...

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...Such register-state duplication is also needed in many other related techniques like threaded multi-path execution [33], speculative data-driven multithreading [28], and thread-level data speculation =-=[30]-=-, etc. For these techniques, the entire register state has to be copied as fast as possible. Consequently, special hardware mechanisms have been proposed to accomplish this task. In our case, although...

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...fers an average speedup of 24% in a set of irregular applications, which is a 19% speedup over state-of-the-art software-controlled prefetching. 1. Introduction Multithreading [1, 32] and prefetching =-=[8, 20, 22]-=- are two major techniques for tolerating ever-increasing memory latency. Multithreading tolerates latency by executing instructions from another concurrent thread when the running thread encounters a ...

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...fers an average speedup of 24% in a set of irregular applications, which is a 19% speedup over state-of-the-art software-controlled prefetching. 1. Introduction Multithreading [1, 32] and prefetching =-=[8, 20, 22]-=- are two major techniques for tolerating ever-increasing memory latency. Multithreading tolerates latency by executing instructions from another concurrent thread when the running thread encounters a ...

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...ds have also been proposed. Examples of them are the multiscalar architecture [29], threadlevel data-speculation (TLDS) [30], threaded multiple path execution (TME) [33], dynamic multithreading (DMT) =-=[2]-=-, slipstream processors [31], and speculative data-driven multithreading (DDMT) [28]. Of course, being able to use the results of speculative threads is appealing. Nevertheless, by caring only data ad...

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...eculatively. There are a number of ways to apply pre-execution, including prefetching data and/or instructions [12, 26], precomputing branch outcomes [15], and pre-computing general execution results =-=[28, 31]-=-. For our purpose, pre-execution is mainly used as a vehicle for speculatively generating data addresses and prefetching---the ultimate computational results are simply ignored. Moreover, unlike sever...

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... mainly used as a vehicle for speculatively generating data addresses and prefetching---the ultimate computational results are simply ignored. Moreover, unlike several recent pre-execution techniques =-=[4, 5, 9, 26, 28, 31, 36]-=- which pre-execute a shortened version of the program, our technique simply works on the original program and hence requires no mechanism to trim the program. In essence, our technique tolerates laten...

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...tching, the main advantage of multithreading is that unlike prefetching, it does not need to predict data addresses in advance which can be a serious challenge in codes with irregular access patterns =-=[20, 26]-=-. Prefetching, however, has a significant advantage that it can improve single-thread performance, unlike multithreading which requires multiple concurrent threads. In this paper, we propose a techniq...

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... mainly used as a vehicle for speculatively generating data addresses and prefetching---the ultimate computational results are simply ignored. Moreover, unlike several recent pre-execution techniques =-=[4, 5, 9, 26, 28, 31, 36]-=- which pre-execute a shortened version of the program, our technique simply works on the original program and hence requires no mechanism to trim the program. In essence, our technique tolerates laten...

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... threadlevel data-speculation (TLDS) [30], threaded multiple path execution (TME) [33], dynamic multithreading (DMT) [2], slipstream processors [31], and speculative data-driven multithreading (DDMT) =-=[28]-=-. Of course, being able to use the results of speculative threads is appealing. Nevertheless, by caring only data addresses but not the final results of pre-execution, our scheme is substantially simp...

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...o generate data addresses and prefetch well ahead of the main execution, we examine a set of applications drawn from four common benchmark suites (SPEC2000 [16], SPEC95 [10], SPLASH-2 [34], and Olden =-=[25]-=-). A large number of cache misses in these applications are due to relatively irregular access patterns involving pointers, hash tables, indirect array references, or a mix of them, which are typicall...

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...to as the approach that tolerates long-latency operations by initiating them early and speculatively. There are a number of ways to apply pre-execution, including prefetching data and/or instructions =-=[12, 26]-=-, precomputing branch outcomes [15], and pre-computing general execution results [28, 31]. For our purpose, pre-execution is mainly used as a vehicle for speculatively generating data addresses and pr...

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... Pipeline Parameters Number of Hardware Contexts 4 Fetch/Decode/Issue/Commit Width 8 Instruction Queue 128 entries Functional Units 8 integer, 6 floating-point; latencies are based on the Alpha 21264 =-=[17]-=- Branch Predictor A McFarling-style choosing branch predictor like the one in the Alpha 21264 [17] Thread Prioritization Policy A modified ICOUNT scheme [32] which favors the main thread Memory Parame...

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...n the values returned from cache misses. The notion of using helper threads to accelerate the main execution was independently introduced in the form of simultaneous subordinate microthreading (SSMT) =-=[7]-=- and assisted execution [11]. In both schemes, helper threads do not directly run the program: Instead, they are designated to perform some specific algorithms such as stride prefetching and self-hist...

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...ed, we can then cancel all wrong-path pre-execution and only keep the one that is on the right path to allow it running ahead of the main execution. A similar idea of executing multiple paths at once =-=[18, 33]-=- has been exploited before to reduce the impact of branch misprediction. Let us illustrate this scheme using the Spec95 benchmark compress. In this application, the function compress() reads a series ...

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... depicts the situation where the address of the next node we want to prefetch is not known until we finish with the current load. To tackle this problem, prefetching techniques based on jump pointers =-=[20, 27]-=- have been proposed to record the address of the node that we would like to prefetch at the current node according to past traversals. These techniques would tolerate the latency of accessing a single...

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...earchers have investigated ways to pre-execute only a subset of instructions (as known as a slice) that lead to performance degradation such as cache misses and branch mispredictions. Zilles and Sohi =-=[35]-=- found that speculation techniques like memory dependency prediction and control independence can be used to significantly reduce the slice size. Recently, a collection of schemes [4, 5, 9, 15, 26, 28...

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... mainly used as a vehicle for speculatively generating data addresses and prefetching---the ultimate computational results are simply ignored. Moreover, unlike several recent pre-execution techniques =-=[4, 5, 9, 26, 28, 31, 36]-=- which pre-execute a shortened version of the program, our technique simply works on the original program and hence requires no mechanism to trim the program. In essence, our technique tolerates laten...

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...cache misses. The notion of using helper threads to accelerate the main execution was independently introduced in the form of simultaneous subordinate microthreading (SSMT) [7] and assisted execution =-=[11]-=-. In both schemes, helper threads do not directly run the program: Instead, they are designated to perform some specific algorithms such as stride prefetching and self-history branch prediction. In co...

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...ed, we can then cancel all wrong-path pre-execution and only keep the one that is on the right path to allow it running ahead of the main execution. A similar idea of executing multiple paths at once =-=[18, 33]-=- has been exploited before to reduce the impact of branch misprediction. Let us illustrate this scheme using the Spec95 benchmark compress. In this application, the function compress() reads a series ...

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...hosen as the platform for this study. An SMT machine allows multiple independent threads to execute simultaneously (i.e. in the same cycle) in different functional units. For example, the Alpha 21464 =-=[13]-=- will be an SMT machine with four threads that can issue up to eight instructions per cycle from one or more threads. Although pre-execution could be applied to other multithreaded architectures as we...

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...latency operations by initiating them early and speculatively. There are a number of ways to apply pre-execution, including prefetching data and/or instructions [12, 26], precomputing branch outcomes =-=[15]-=-, and pre-computing general execution results [28, 31]. For our purpose, pre-execution is mainly used as a vehicle for speculatively generating data addresses and prefetching---the ultimate computatio...

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... mainly used as a vehicle for speculatively generating data addresses and prefetching---the ultimate computational results are simply ignored. Moreover, unlike several recent pre-execution techniques =-=[4, 5, 9, 26, 28, 31, 36]-=- which pre-execute a shortened version of the program, our technique simply works on the original program and hence requires no mechanism to trim the program. In essence, our technique tolerates laten...

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...ended algorithm [22] for prefetching these references was used. For the remaining five applications, we experimented with the greedy prefetching and jump-pointer prefetching proposed by Luk and Mowry =-=[20, 21]-=- as well as the extensions of jump-pointer prefetching (full jumping, chain jumping, and root jumping) proposed by Roth and Sohi [27]. In all cases, a wide range of prefetching distances (whenever app...

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...pre-execution can be employed to generate data addresses and prefetch well ahead of the main execution, we examine a set of applications drawn from four common benchmark suites (SPEC2000 [16], SPEC95 =-=[10]-=-, SPLASH-2 [34], and Olden [25]). A large number of cache misses in these applications are due to relatively irregular access patterns involving pointers, hash tables, indirect array references, or a ...

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...ting softwarecontrolled pre-execution in future SMT machines. 8. Acknowledgments I thank Joel Emer's encouragement of pursuing a softwarebased approach to pre-execution (see his HPCA-7 keynote speech =-=[14]-=- for the philosophy behind). Yuan Chou, Robert Cohn, Joel Emer, and Steve Wallace gave insightful comments on early drafts of the paper. In addition, I thank the Asim team for supporting the simulator...

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...single chain if the traversal order is fairly static over time and the overhead of maintaining those jump pointers does not overwhelm the benefit. Recently, a technique called multi-chain prefetching =-=[19]-=- has been proposed to attack the pointer-chasing problem from a different angle. Instead of prefetching pointer chains one at a time, this technique prefetches multiple pointer chains that will be vis...