DMCA
Detailed routing architectures for embedded programmable logic IP cores (2001)
Venue: | In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays |
Citations: | 10 - 0 self |
Citations
460 |
Architecture and CAD for Deep-Submicron FPGAs”,
- Betz, Rose, et al.
- 1999
(Show Context)
Citation Context ... of each horizontal and verticalchannel is a switch block that comprises of 50% pass-transistors and 50% tri-state buffers (see [10]). Connection-block and switchblock populations are both 100% (see =-=[11]-=-). 3. RECTANGULAR SWITCH BLOCK At the intersection of each horizontal channel and each vertical channel lies a switch block. Each switch block provides for programmable connections between tracks of t... |
321 | FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
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Citation Context ...ted in commercially available stand-alone FPGAs. Half of the circuits were sequential, and half were combinational. Each circuit was optimized and technologymapped using SIS [14] and Flowmap/Flowpack =-=[15]-=-. The logic elements were then packed to logic clusters using Vpack [16] and timing-driven placement and routing was performed using a modified version of VPR [16]. For each circuit and architecture, ... |
113 |
Logic synthesis and optimization benchmarks. Version 3.0
- Yang
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Citation Context ...LTS To investigate the suitability of the new switch block family, we used an experimental approach. Twenty benchmark circuits from the Microelectronics Corporation of North Carolina (MCNC) were used =-=[13]-=-. Because we were primarily interested in circuits which would fit into an embedded programmable logic core, we chose circuits which were approximately 10% of the size of circuits which could be imple... |
112 |
The Programmable Logic Data
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Citation Context ...very significant part of the routing flexibility, the design of a good switch block is of the utmost importance. Thus, there has been considerable work developing efficient switch block architectures =-=[4]-=-[5][6][7]. All of the previous switch blocks are square; in other words, they assume the same number of incident tracks for all sides. In our environment, however, vertical and horizontal channels wil... |
95 | Timing-driven placement for FPGAs. In: - Marquardt, Betz, et al. - 2000 |
61 | Architecture and algorithms for fieldprogrammable gate arrays with embedded memory,”
- Wilton
- 1997
(Show Context)
Citation Context ...ignificant part of the routing flexibility, the design of a good switch block is of the utmost importance. Thus, there has been considerable work developing efficient switch block architectures [4][5]=-=[6]-=-[7]. All of the previous switch blocks are square; in other words, they assume the same number of incident tracks for all sides. In our environment, however, vertical and horizontal channels will ofte... |
55 | FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density”,
- Betz, Rose
(Show Context)
Citation Context ...e channel are staggered relative to each other [9]. At the intersection of each horizontal and verticalchannel is a switch block that comprises of 50% pass-transistors and 50% tri-state buffers (see =-=[10]-=-). Connection-block and switchblock populations are both 100% (see [11]). 3. RECTANGULAR SWITCH BLOCK At the intersection of each horizontal channel and each vertical channel lies a switch block. Each... |
38 | Universal switch modules for FPGA design.
- Chang, Wong, et al.
- 1996
(Show Context)
Citation Context ...y significant part of the routing flexibility, the design of a good switch block is of the utmost importance. Thus, there has been considerable work developing efficient switch block architectures [4]=-=[5]-=-[6][7]. All of the previous switch blocks are square; in other words, they assume the same number of incident tracks for all sides. In our environment, however, vertical and horizontal channels will o... |
25 |
SIS: A System for Sequential Circuit Analysis”,
- Sentovich
- 1990
(Show Context)
Citation Context ...ts which could be implemented in commercially available stand-alone FPGAs. Half of the circuits were sequential, and half were combinational. Each circuit was optimized and technologymapped using SIS =-=[14]-=- and Flowmap/Flowpack [15]. The logic elements were then packed to logic clusters using Vpack [16] and timing-driven placement and routing was performed using a modified version of VPR [16]. For each ... |
18 | Automatic Generation of FPGA Routing Architectures from HighLevel Descriptions
- Betz, Rose
- 2000
(Show Context)
Citation Context ... we assume, without loss of generality, that t y > t x. We assume a segmented architecture in which every track spans 4 logic clusters. Tracks of the same channel are staggered relative to each other =-=[9]-=-. At the intersection of each horizontal and verticalchannel is a switch block that comprises of 50% pass-transistors and 50% tri-state buffers (see [10]). Connection-block and switchblock population... |
16 | A Detailed Router for Allocating Wire Segments - Lemieux, Brown - 1993 |
15 |
A New Switch Block for Segmented FPGAs”
- Masud, Wilton
- 1999
(Show Context)
Citation Context ...ificant part of the routing flexibility, the design of a good switch block is of the utmost importance. Thus, there has been considerable work developing efficient switch block architectures [4][5][6]=-=[7]-=-. All of the previous switch blocks are square; in other words, they assume the same number of incident tracks for all sides. In our environment, however, vertical and horizontal channels will often h... |
4 |
LSI Logic ASICs to add Programmable Logic Cores
- Matsumoto
- 1999
(Show Context)
Citation Context ... a programmable logic core. In this case, the programmable logic core is simply another core that the system-on-a-chip designer can buy from a third party. Already, several companies offer such cores =-=[1]-=-[2]. The potential benefits of integrating fixed and programmable logic described above are so compelling that we feel that the ability to make post-fabrication changes in a fixed-function ASIC will e... |
2 |
Actel Plans to Produce FPGAs as ASIC
- Matsumoto
- 1999
(Show Context)
Citation Context ...programmable logic core. In this case, the programmable logic core is simply another core that the system-on-a-chip designer can buy from a third party. Already, several companies offer such cores [1]=-=[2]-=-. The potential benefits of integrating fixed and programmable logic described above are so compelling that we feel that the ability to make post-fabrication changes in a fixed-function ASIC will even... |
1 |
Directional and Non-Uniformity
- Betz, Rose
- 1996
(Show Context)
Citation Context ...s of this paper. Specifically, this paper focuses on two aspects: Logic Block Switch Block Narrow Channel Wide Channel Figure 2: an FPGA with unequal horizontal and vertical channel capacities. 1. In =-=[3]-=-, it was suggested that for a rectangular FPGA, channels in the long direction should have more tracks than channels in the narrow direction (as shown in Figure 2). On average, signals will have to tr... |