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...hboring threads [21]. Simulation Infrastructure: We simulate a 4-core CMP using a trace-driven, cycleaccurate simulator, where each core is an out-of-order superscalar processor based on SimpleScalar =-=[22]-=-. The tracegeneration portion of this infrastructure is based on the PIN instrumentation tool [23], and the architectural simulation portion TABLE III COVERAGE OF LOOPS PARALLELIZED. Benchmark Coverag...

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...cleaccurate simulator, where each core is an out-of-order superscalar processor based on SimpleScalar [22]. The tracegeneration portion of this infrastructure is based on the PIN instrumentation tool =-=[23]-=-, and the architectural simulation portion TABLE III COVERAGE OF LOOPS PARALLELIZED. Benchmark Coverage (%) No. of loops I I + II I + II + III 1 I + II I + II + III milc 13 79 79 5 22 22 lbm 0 100 100...

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...rove performance of general-purpose applications. Potential for Thread-level parallelism 1(TLP) has been well understood in older benchmark suites like SPEC 2000 [18]. However with the current trend =-=[4]-=-towards more parallel applications, it is not clear if the newer general-purpose benchmarks in SPEC 2006 [19] exhibit more potential for Thread-Level Parallelism (TLP). Automatic compiler parallelizat...

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...ional compilers; but with the help of TLS, the compiler can parallelize this loop speculatively and relying on the underlying hardware to detect and enforce inter-thread data dependences at run-time. =-=[5]-=-, [6], [7], [8], [9], [10] Though TLS has been extensively studied in the past, it is not clear how much TLS could benefit more recent benchmarks such as SPEC 2006 [11], which represent a different cl...

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...ilers; but with the help of TLS, the compiler can parallelize this loop speculatively and relying on the underlying hardware to detect and enforce inter-thread data dependences at run-time. [5], [6], =-=[7]-=-, [8], [9], [10] Though TLS has been extensively studied in the past, it is not clear how much TLS could benefit more recent benchmarks such as SPEC 2006 [11], which represent a different class of app...

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... compilers; but with the help of TLS, the compiler can parallelize this loop speculatively and relying on the underlying hardware to detect and enforce inter-thread data dependences at run-time. [5], =-=[6]-=-, [7], [8], [9], [10] Though TLS has been extensively studied in the past, it is not clear how much TLS could benefit more recent benchmarks such as SPEC 2006 [11], which represent a different class o...

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... the help of TLS, the compiler can parallelize this loop speculatively and relying on the underlying hardware to detect and enforce inter-thread data dependences at run-time. [5], [6], [7], [8], [9], =-=[10]-=- Though TLS has been extensively studied in the past, it is not clear how much TLS could benefit more recent benchmarks such as SPEC 2006 [11], which represent a different class of applications. Some ...

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...rtain loops that the compiler will not normally automatically parallelize. Such manual analysis combined with simple loop transformations has been shown to create more parallelism in previous studies =-=[16, 5, 12]-=-. In this paper our aim is to present the TLS performance as an automatic parallelizing compiler without manual intervention. In [10] Kejariwal et al used their framework of analysis to study SPEC 200...

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... with the help of TLS, the compiler can parallelize this loop speculatively and relying on the underlying hardware to detect and enforce inter-thread data dependences at run-time. [5], [6], [7], [8], =-=[9]-=-, [10] Though TLS has been extensively studied in the past, it is not clear how much TLS could benefit more recent benchmarks such as SPEC 2006 [11], which represent a different class of applications....

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...nted a study on the limits of TLS performance on some SPECint95 benchmarks. The impact of compiler optimizations and the TLS overhead were not taken into account in that study. Similarly, Warg et. al =-=[15]-=- presented a limit study for module-level parallelism in object-oriented programs. In contrast, in this study, our aim is to illustrate the realizable performance of TLS using a state-of-the-art TLS c...

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...odel used can be found in [6]. Frequently occurring memory-based dependences and registerbased scalar dependences are synchronized by inserting special instructions as shown in Figure 2(b) similar to =-=[8]-=-, [7]. Compilation Infrastructure Our compiler infrastructure is built on Open64 3.0 Compiler [19], an industrial-strength open-source compiler targeting Intel’s Itanium Processor Family (IPF). To cre...

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...evious work focused on exploiting parallelism using TLS at a single loop nest level, relatively little has been done to exploit parallelism at multiple nested loop levels simultaneously. Renau et. al =-=[17]-=- proposed hardware-based techniques to determine how to allocate cores to threads that are extracted from different nesting levels; while our paper proposes compiler techniques that statically determi...

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...se, the compiler first estimates the parallel performance of each loop, then choose to parallelize a set of loops that maximize the overall program performance based on such estimation. Previous work =-=[20]-=- builds the performance estimation based on detailed data dependence profiling information, as shown in Figure 9. Thus, the achievable performance of speculative parallel threads is tied with the accu...

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...ograms. In contrast, in this study, our aim is to illustrate the realizable performance of TLS using a state-of-the-art TLS compiler, while taking into account various TLS overheads. Kejariwal et. al =-=[16]-=- separated the speedup achievable through traditional thread-level parallelism from that of TLS using the SPEC2000 benchmarks assuming an oracle TLS mechanism. They [12] later extended their study to ...

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...s of loops is beyond the scope of our paper. Compiler-based scheduling schemes for nested loops have been studied in the past to support nested DOALL and DOACROSS loops. We extend the OPTAL algorithm =-=[25]-=- that was originally designed for core allocation for nested DOALL and DOACROSS loops to allocate cores for TLS loops at compile time. A. Speculative OPTAL algorithm The OPTAL algorithm uses a dynamic...

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...ks using 8 cores when we extend TLS on multiple loop levels as opposed to restricting to a single loop level. I. INTRODUCTION With the advent of multi-threaded (e.g. simultaneous multithreading (SMT) =-=[1]-=-, hyper-threading [2]) and/or multi-core (e.g. chip multiprocessors (CMP) [3], [4]) architectures, now the challenge is to utilize these architectures to improve performance of general-purpose applica...

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...tricting to a single loop level. I. INTRODUCTION With the advent of multi-threaded (e.g. simultaneous multithreading (SMT) [1], hyper-threading [2]) and/or multi-core (e.g. chip multiprocessors (CMP) =-=[3]-=-, [4]) architectures, now the challenge is to utilize these architectures to improve performance of general-purpose applications. Automatic compiler parallelization techniques have been developed and ...

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... been extensively studied in the past, it is not clear how much TLS could benefit more recent benchmarks such as SPEC 2006 [11], which represent a different class of applications. Some recent studies =-=[12]-=- on SPEC 2006 benchmarks have shown very limited potential for TLS (less than 1%) under very conservative assumptions. In this paper, we re-examine some of these issues and give a more realistic asses...

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...tial for TLS than those studies. Kejariwal et. al [12] did not take into account the effect of compiler optimizations that could improve the performance of TLS, while previous studies [10], [7], [8], =-=[13]-=- have shown that compiler-based loop selection and optimizations, such as code scheduling, can significantly improve the efficiency of TLS. Furthermore, Kejariwal et. al [12] only considered innermost...

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... TLS only on a single loop level. 1 Introduction With the advent of multi-threaded (e.g. simultaneous multi-threading (SMT) [7], hyper-threading [9])and/or multi-core (e.g. chip multiprocessors (CMP) =-=[8, 3]-=-) architectures, the challenge now is to utilize these architectures to improve performance of general-purpose applications. Potential for Thread-level parallelism 1(TLP) has been well understood in ...

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...in probabilistic information through data dependence profile. In this section, we conduct detailed analysis on interthread memory-based dependence using profiling information.by such synchronization =-=[18]-=-. Fig. 6. The coverage of loops with inter-thread memory-based data dependences less than a certain probability. We classify benchmarks based on the combined coverage of loops with different number of...

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...warding path introduced by the synchronization [7], [13]; (iii) computation and usage of reduction and reduction-like variables are transformed to avoid speculation failure and reduce synchronization =-=[21]-=-; and (iv) consecutive loop iterations are merged to balance the workload between neighboring threads [21]. Simulation Infrastructure: We simulate a 4-core CMP using a trace-driven, cycleaccurate simu...