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...s, full-scan versions of ISCAS-89 benchmark circuits have been used. The ISCAS-89 benchmark contains a number of circuits but only the largest seven sequential circuits are used in this work. MINTEST =-=[98]-=- generated test sets using both static and dynamic compaction have been used as 55sTable 4.1: Details of ISCAS-89 benchmarks and test sets used MINTEST Static compacted MINTEST Dynamic compacted Test ...

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...ains architecture that uses a correction circuit [68]. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding =-=[70, 71, 72, 73, 74, 75]-=-. The original test compression methodology using LFSR reseeding was proposed by Koenemann [70]. A seed is loaded into an LFSR and then the LFSR is run in an autonomous mode to fill a set of scan chai...

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...ains architecture that uses a correction circuit [68]. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding =-=[70, 71, 72, 73, 74, 75]-=-. The original test compression methodology using LFSR reseeding was proposed by Koenemann [70]. A seed is loaded into an LFSR and then the LFSR is run in an autonomous mode to fill a set of scan chai...

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...ed in the comparison according to the comparison criteria. Table 4.14 presents comparison with a MUXs network based decompressor [90]. This scheme also uses a static reconfiguration approach. ATLANTA =-=[99]-=- ATPG tool has been used to generate the test sets and 100 scan chains are used for all circuits. Separate comparisons are given according to M value, total vectors count, and the highest achieved com...

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...are broadcasted to multiple scan chains within a core or across multiple cores. The broadcast mode is used when the vectors going into multiple chains are compatible. Illinois Scan Architecture (ISA) =-=[18]-=- was 13sintroduced to reduce data volume and test application time by splitting a given scan chain into multiple segments. Since a majority of the bits in ATPG patterns are don’t care bits, there are ...

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...circuit under test. Most compression techniques of this type compress TD without requiring any structural information about the embedded cores. Proposed compression schemes include statistical coding =-=[39, 40]-=-, 18sselective Huffman coding [41], mixed run-length and Huffman coding [42], Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-...

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...The Embedded Deterministic Test method [76] uses a ring generator which is an alternative linear finite state machine that offers some advantages over an LFSR. Another group of compression techniques =-=[77, 78]-=- breaks the single long scan chain down into multiple internal scan chains that can be simultaneously sourced. Because the number of I/O pins available from the ATE is limited, a decompression network...

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...s don’t cares), the corresponding seeds can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. The Embedded Deterministic Test method =-=[76]-=- uses a ring generator which is an alternative linear finite state machine that offers some advantages over an LFSR. Another group of compression techniques [77, 78] breaks the single long scan chain ...

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...ssion techniques based on LZ77, LZW and test-data realignment methods are proposed by Pomeranz and Reddy [63], Knieser et al. [64] and Wolff 20sand Papachristou [65], respectively. Li et al. proposed =-=[66]-=- a compression technique using dictionary with fixed-length indices for multiple-scan chain designs. A hybrid coding scheme, combining alternating run-length and dictionary-based encoding, is proposed...

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...ains architecture that uses a correction circuit [68]. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding =-=[70, 71, 72, 73, 74, 75]-=-. The original test compression methodology using LFSR reseeding was proposed by Koenemann [70]. A seed is loaded into an LFSR and then the LFSR is run in an autonomous mode to fill a set of scan chai...

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...sed compression schemes include statistical coding [39, 40], 18sselective Huffman coding [41], mixed run-length and Huffman coding [42], Golomb coding [43], frequency-directed run-length (FDR) coding =-=[44]-=-, geometric shape-based encoding [45], alternating run-length coding using FDR [46], extended FDR coding [47], MTC coding [48], variable-input Huffman coding (VIHC) coding[49], ninecoded compression t...

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...echniques of this type compress TD without requiring any structural information about the embedded cores. Proposed compression schemes include statistical coding [39, 40], 18sselective Huffman coding =-=[41]-=-, mixed run-length and Huffman coding [42], Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-length coding using FDR [46], exte...

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...ains architecture that uses a correction circuit [68]. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding =-=[70, 71, 72, 73, 74, 75]-=-. The original test compression methodology using LFSR reseeding was proposed by Koenemann [70]. A seed is loaded into an LFSR and then the LFSR is run in an autonomous mode to fill a set of scan chai...

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...and data memory are limited. Therefore, design and test engineers need new techniques for decreasing data volume. Built-in self-test (BIST) has emerged as an alternative to ATE-based external testing =-=[7]-=-. BIST offers a number of key advantages. It allows precomputed test sets to be embedded in the test sequences generated by on-chip hardware. It supports test reuse, at-speed testing, and protects int...

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...g [47], MTC coding [48], variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding [51], mutation codes =-=[52]-=-, packet-based codes [53] and nonlinear combinational codes [54]. A multi-level Huffman coding scheme that utilizes a LFSR for random filling has been proposed by Kavousianos et al. [55] while Polian ...

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...they are compatible. A segmented addressable scan architecture is proposed by Al-Yamani et al. [25] that incorporates some of the basic concepts from Illinois scan [18] and from scan segment decoding =-=[24, 26]-=-. It allows multiple segments to be loaded simultaneously while maintaining the freedom of changing which of the segments are grouped together within a give test pattern. Unlike the technique of Samar...

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... run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-length coding using FDR [46], extended FDR coding [47], MTC coding [48], variable-input Huffman coding (VIHC) coding=-=[49]-=-, ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding [51], mutation codes [52], packet-based codes [53] and nonlinear combinational codes [54]. A ...

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...oding [41], mixed run-length and Huffman coding [42], Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-length coding using FDR =-=[46]-=-, extended FDR coding [47], MTC coding [48], variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding [...

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...ains architecture that uses a correction circuit [68]. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding =-=[70, 71, 72, 73, 74, 75]-=-. The original test compression methodology using LFSR reseeding was proposed by Koenemann [70]. A seed is loaded into an LFSR and then the LFSR is run in an autonomous mode to fill a set of scan chai...

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...he concept of scan chain compatibility and the associated fan-out structure have been utilized in a number of papers [78, 18, 82, 22] since the broadcast scan architecture was presented by Lee et al. =-=[95]-=-. It is also referred to as ’test width compression’ [77, 68]. Let b(k, i, j) denote the data bit that is shifted into the j th flip-flop of i th scan chain for the k th test vector. The compatibility...

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...circuit under test. Most compression techniques of this type compress TD without requiring any structural information about the embedded cores. Proposed compression schemes include statistical coding =-=[39, 40]-=-, 18sselective Huffman coding [41], mixed run-length and Huffman coding [42], Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-...

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...ct output vector [62]. Test-data compression techniques based on LZ77, LZW and test-data realignment methods are proposed by Pomeranz and Reddy [63], Knieser et al. [64] and Wolff 20sand Papachristou =-=[65]-=-, respectively. Li et al. proposed [66] a compression technique using dictionary with fixed-length indices for multiple-scan chain designs. A hybrid coding scheme, combining alternating run-length and...

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... requiring any structural information about the embedded cores. Proposed compression schemes include statistical coding [39, 40], 18sselective Huffman coding [41], mixed run-length and Huffman coding =-=[42]-=-, Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-length coding using FDR [46], extended FDR coding [47], MTC coding [48], var...

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...variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding [51], mutation codes [52], packet-based codes =-=[53]-=- and nonlinear combinational codes [54]. A multi-level Huffman coding scheme that utilizes a LFSR for random filling has been proposed by Kavousianos et al. [55] while Polian et al. [56] proposes use ...

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...ic shape-based encoding [45], alternating run-length coding using FDR [46], extended FDR coding [47], MTC coding [48], variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique =-=[50]-=-, Burrows-Wheeler transform based compression [?], arithmetic coding [51], mutation codes [52], packet-based codes [53] and nonlinear combinational codes [54]. A multi-level Huffman coding scheme that...

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...iments 4.1 Experimental Setup All programs are written in C and compiled under Linux. HOPE simulator [96] was used for fault simulations and graph coloring implementation provided by Joseph Culberson =-=[97]-=- have been used. A variety of algorithms exist for graph coloring but only DSATUR has been used in this work because of ease of use and reasonable quality of results. For generation of relaxed atomic ...

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...stical coding [39, 40], 18sselective Huffman coding [41], mixed run-length and Huffman coding [42], Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding =-=[45]-=-, alternating run-length coding using FDR [46], extended FDR coding [47], MTC coding [48], variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique [50], Burrows-Wheeler transf...

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...The Embedded Deterministic Test method [76] uses a ring generator which is an alternative linear finite state machine that offers some advantages over an LFSR. Another group of compression techniques =-=[77, 78]-=- breaks the single long scan chain down into multiple internal scan chains that can be simultaneously sourced. Because the number of I/O pins available from the ATE is limited, a decompression network...

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...th and Huffman coding [42], Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-length coding using FDR [46], extended FDR coding =-=[47]-=-, MTC coding [48], variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding [51], mutation codes [52], ...

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...ircuits with MINTEST test sets without compaction, Hayashi et al. [60] use X-maximal program for test set generation with scan chains lengths varying between 16 and 64 in powers of 2, and Tang et al. =-=[101]-=- do not specify the specifics of test sets and all results are reported with 256 scan chains except for s15850, where 128 are used. The proposed technique achieves higher compression with most of the ...

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... alternating run-length and dictionary-based encoding, is proposed by Wurtenberger et al. [67], and another dictionary scheme based on multiple scan chains architecture that uses a correction circuit =-=[68]-=-. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding [70, 71, 72, 73, 74, 75]. The original test compressi...

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...t compaction is the process of reducing the number of test vectors in a test set to the minimum while achieving the desired fault coverage. Finding the smallest set is proven to be an NP-hard problem =-=[14]-=-, therefore, heuristics are used to find a reasonable solution [15]. There are two main categories of test compaction techniques: static compaction and dynamic compaction. In static compaction, the te...

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...mplexity. Bottleneck vector are decomposed into a small subset of test vectors each satisfying the tester channel constraint M, using an efficient relaxation-based test vector decomposition technique =-=[11]-=-. Then, decomposed test vectors are partitioned minimizing the number of partitions. By varying M with a given input test data set for a specified number of internal scan chains, the proposed techniqu...

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...The download from a workstation storing a test set to the user interface workstation attached to an ATE is often accomplished through a network. The download may take several tens of minutes to hours =-=[4]-=-. The test set is then transferred from the user interface workstation of an ATE to the main pattern memory through a dedicated high speed bus. The latter transfer usually takes several minutes. The t...

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...ngs in test application time. 2.2 Scan Architectures Several enhancements to the existing scan architecture have been proposed in the literature for test volume, time and power reductions. Lee et al. =-=[17]-=- present a scan broadcasting scheme where ATPG patterns are broadcasted to multiple scan chains within a core or across multiple cores. The broadcast mode is used when the vectors going into multiple ...

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...n of compatibility allows for significant additional compaction leading to gains in data volume reduction. The scan architectures mentioned before are serial. An alternate is Random Access Scan (RAS) =-=[27, 28]-=-. In RAS, flip-flops work as addressable memory elements in the test mode, similar to a random access memory. This approach reduces the time of setting and observing the flip-flop states but requires ...

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...ead of an XOR network, to construct such a decompression architecture [76]. Many multiple-scan architecture based compression schemes uses extra control logic to reconfigure the decompression network =-=[84, 54, 85]-=-. For the price of some significant amount of extra control hardware, these approaches can provide additional flexibility in enhancing the compression ratio. Oh et al. [86] improves upon the ILS compr...

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...ding [42], Golomb coding [43], frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-length coding using FDR [46], extended FDR coding [47], MTC coding =-=[48]-=-, variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding [51], mutation codes [52], packet-based code...

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...y. This work proposes a test vector compression scheme that is based on a reconfigurable broadcast scan approach that drives N scan chains using M tester channels. Using direct compatibility analysis =-=[10]-=-, test vectors are classified into ‘acceptable’ and ‘bottleneck’ vectors. Acceptable vectors are those that can be driven by M tester channels while bottleneck vectors are those that cannot be driven ...

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...ompaction. Another scan architecture, proposed by Xiang et al. [23], orders the scan cells and connects them based on their functional interaction. In the circular scan scheme by Arslan and Orailoglu =-=[24]-=-, a decoder is used to address different scan chains at different times. This increases the number of possible scan chains (2 N−1 for an N-input decoder). Also, the output of each scan chain is reconn...

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... application time, and power consumption are all reduced at once. Only one segment of the scan chain is controlled and observed at a time. A reconfigurable scheme is introduced by Samaranayake et al. =-=[22]-=- that uses mapping logic to control the connection of multiple scan chains. This increases 14sthe chances of compatibility between multiple chains and hence makes room for additional compaction. Anoth...

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... of setting and observing the flip-flop states but requires a large overhead both in gates and test pins. Despite these drawbacks, RAS has been researched in recent years. The research by Baik et al. =-=[29]-=- shows that RAS based technique allows test 15sapplication time and data volume to be greatly reduced, besides over 99% power reduction. However, it shows that this method compromises the test cost wi...

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...ngth indices to generate all distinct output vector [62]. Test-data compression techniques based on LZ77, LZW and test-data realignment methods are proposed by Pomeranz and Reddy [63], Knieser et al. =-=[64]-=- and Wolff 20sand Papachristou [65], respectively. Li et al. proposed [66] a compression technique using dictionary with fixed-length indices for multiple-scan chain designs. A hybrid coding scheme, c...

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... compression for BIST based test generation process [10]. Width reduction for BIST has been achieved by merging directly and inversely compatible inputs [10], by merging decoder (d)-compatible inputs =-=[79]-=-, and, finally, by merging combinational (C)-compatible inputs [80]. In the ILS [18], a simple fanout based network is used. Though simple and low-cost, this type of network is highly restrictive, as ...

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...uction for BIST has been achieved by merging directly and inversely compatible inputs [10], by merging decoder (d)-compatible inputs [79], and, finally, by merging combinational (C)-compatible inputs =-=[80]-=-. In the ILS [18], a simple fanout based network is used. Though simple and low-cost, this type of network is highly restrictive, as it forces the internal scan chains to receive the exact same values...

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...th inputs and outputs. test set. Partitioning enables achieving high compression without requiring ’bloated’ test sets consisting of a very large number of test vectors with a very few specified bits =-=[93, 94]-=-. 2. Those scan vectors (labeled as bottleneck vectors) that limit achieving a desired M are decomposed using an efficient relaxation-based test vector decomposition technique [11] in an incremental m...

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...sample of MUX connections for implementing partitioning 54 Internal Scan Chains (N)sChapter 4 Experiments 4.1 Experimental Setup All programs are written in C and compiled under Linux. HOPE simulator =-=[96]-=- was used for fault simulations and graph coloring implementation provided by Joseph Culberson [97] have been used. A variety of algorithms exist for graph coloring but only DSATUR has been used in th...

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...the captured response of the previous patterns in the flip-flops is used as a template and modified by a circular shift for subsequent pattern. Mudlapur et al. presents a unique RAS cell architecture =-=[31, 32]-=- that aims to minimize the routing complexity. Another novel scan architecture called Progressive Random Access Scan (PRAS) [33] and the associated test application methods have been proposed. It has ...

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... using dictionary with fixed-length indices for multiple-scan chain designs. A hybrid coding scheme, combining alternating run-length and dictionary-based encoding, is proposed by Wurtenberger et al. =-=[67]-=-, and another dictionary scheme based on multiple scan chains architecture that uses a correction circuit [68]. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. Th...

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...of the regularity and periodicity of scan chains. Another scheme for selective triggering of scan segments was proposed by Sharifi et al. [20]. A novel scheme was presented by Sinanoglu and Orailoglu =-=[21]-=- to reduce test power consumption by freezing scan segments that don’t have care bits in the next test stimulus. By only loading the segments that have care bits, test data volume, application time, a...

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...nt pattern. Mudlapur et al. presents a unique RAS cell architecture [31, 32] that aims to minimize the routing complexity. Another novel scan architecture called Progressive Random Access Scan (PRAS) =-=[33]-=- and the associated test application methods have been proposed. It has a structure similar to static random access memory. Test vector ordering and Hamming distance reduction are proposed to minimize...

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...tural information about the embedded cores. Proposed compression schemes include statistical coding [39, 40], 18sselective Huffman coding [41], mixed run-length and Huffman coding [42], Golomb coding =-=[43]-=-, frequency-directed run-length (FDR) coding [44], geometric shape-based encoding [45], alternating run-length coding using FDR [46], extended FDR coding [47], MTC coding [48], variable-input Huffman ...

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...ains architecture that uses a correction circuit [68]. Shi et al. [69] uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding =-=[70, 71, 72, 73, 74, 75]-=-. The original test compression methodology using LFSR reseeding was proposed by Koenemann [70]. A seed is loaded into an LFSR and then the LFSR is run in an autonomous mode to fill a set of scan chai...

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...ders [?]. A majority of bits in test patterns are unspecified. Prior to the rise of test data volume and test application time, the typical industry practice was to randomly fill the unspecified bits =-=[9]-=-. Test compression technology creatively discovers alternatives for handling these randomly filled bits, which decreases test data volume and test application time efficiency. Because the goal of test...

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...od compromises the test cost with a high hardware overhead and the practicality of RAS architecture implementation were not addressed. A modified RAS scheme has been described by Arslan and Orailoglu =-=[30]-=- in which the captured response of the previous patterns in the flip-flops is used as a template and modified by a circular shift for subsequent pattern. Mudlapur et al. presents a unique RAS cell arc...

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...nouts to form the inverter-interconnect based network in approach by Rao et al. [81]. An enhancement of the Illinois Scan Architecture for use with multiple scan inputs is presented by Shah and Patel =-=[82]-=- 22swhile Ashiouei et al. [83] presents a technique for balanced parallel scan to improve ILS technique eliminating the need to scan vectors in serially. In the Scan Chain Concealment approach [77], a...

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...th inputs and outputs. test set. Partitioning enables achieving high compression without requiring ’bloated’ test sets consisting of a very large number of test vectors with a very few specified bits =-=[93, 94]-=-. 2. Those scan vectors (labeled as bottleneck vectors) that limit achieving a desired M are decomposed using an efficient relaxation-based test vector decomposition technique [11] in an incremental m...

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...of the faults. Other proposals can be seen as the logical extension to the above approach. Inverters are coupled with fanouts to form the inverter-interconnect based network in approach by Rao et al. =-=[81]-=-. An enhancement of the Illinois Scan Architecture for use with multiple scan inputs is presented by Shah and Patel [82] 22swhile Ashiouei et al. [83] presents a technique for balanced parallel scan t...

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...ess in dynamic compaction. Compaction is not discussed in detail here as the focus of this work is test data compression. The gains in test data volume reduction by using compaction alone are limited =-=[16]-=-. However, some form of compaction is used implicitly or explicitly by many test data compression techniques to reduce the number of distinct test vectors to be applied, thus achieving greater compres...

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...ng the segments into a single long scan chain. The fact that a majority of the ATPG bits (95-99%) [9] are don’t care bits makes ISA an attractive solution for data volume and test time. Huang and Lee =-=[19]-=- introduced a token scan architecture to gate the clock to different scan segments while taking advantage of the regularity and periodicity of scan chains. Another scheme for selective triggering of s...

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...ion of multiple scan chains. This increases 14sthe chances of compatibility between multiple chains and hence makes room for additional compaction. Another scan architecture, proposed by Xiang et al. =-=[23]-=-, orders the scan cells and connects them based on their functional interaction. In the circular scan scheme by Arslan and Orailoglu [24], a decoder is used to address different scan chains at differe...

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... Along with a X-tolerant compactor, PRAVS, achieves greater test data/time reductions than conventional RAS. Recently, compression schemes utilizing RAS architecture have been proposed. Cocktail Scan =-=[37]-=-, a hybrid method unlike the LFSR-based hybrid BIST, adopts a two-phase approach to perform scan test in which all test data are supplied from the 16sATE. However, for test patterns, instead of supply...

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...ashion and they are reordered and compressed with some proposed strategies to reduce data volume, number of bit flips, and consequently, test energy. A compression/scan codesign approach by Hu et al. =-=[38]-=- achieves the goal of simultaneously reducing test data volume, power dissipation and application time by exploiting the characteristics of both variable-to-fixed run-length coding and random access s...

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...t-based codes [53] and nonlinear combinational codes [54]. A multi-level Huffman coding scheme that utilizes a LFSR for random filling has been proposed by Kavousianos et al. [55] while Polian et al. =-=[56]-=- proposes use of an evolutionary heuristic with a Huffman code based technique. A scheme based on MICRO (Modified Input reduction and CompRessing One block) code is proposed by Chun et al. [57] that u...

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...ors is shortened in a manner that the code length for rare scan vectors is designed to be double of that for frequent ones. A compression scheme extending run-length coding is presented by Doi et al. =-=[61]-=- that employs two techniques: scan polarity adjustment and pinpoint test relaxation. Given a test set for a full-scan circuit, scan polarity adjustment selectively flips the values of some scan cells ...

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...length and dictionary-based encoding, is proposed by Wurtenberger et al. [67], and another dictionary scheme based on multiple scan chains architecture that uses a correction circuit [68]. Shi et al. =-=[69]-=- uses dictionary-based encoding on single or sequences of scan-inputs. The next class of techniques are ones using LFSR reseeding [70, 71, 72, 73, 74, 75]. The original test compression methodology us...

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...compression network [84, 54, 85]. For the price of some significant amount of extra control hardware, these approaches can provide additional flexibility in enhancing the compression ratio. Oh et al. =-=[86]-=- improves upon the ILS compression technique using fan-out scan chains, creating a solution in which dependencies caused by the fan-out scan chain structure do not interfere in the application of test...

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...88], the basic idea of which is to target the minority specified bits (either a 1 or 0) in scan slices for compression. A compression scheme using reconfigurable linear decompressor has been proposed =-=[89]-=-. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for designing the reconfigurable network. The proposed scheme can be implemented in conjunction ...

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...ing these circuits maybe expensive and may require considerable redesign. Test resource partitioning (TRP) offers a promising solution to these problems by moving some test resources from ATE to chip =-=[8]-=-. One of the possible TRP approaches is based on the use of test data compression and on-chip decompression, hence reducing test data volume, decreasing testing time, and allowing the use of slower te...

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...in a test set to the minimum while achieving the desired fault coverage. Finding the smallest set is proven to be an NP-hard problem [14], therefore, heuristics are used to find a reasonable solution =-=[15]-=-. There are two main categories of test compaction techniques: static compaction and dynamic compaction. In static compaction, the test set is reduced after it has been generated. On the other hand, i...

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...the captured response of the previous patterns in the flip-flops is used as a template and modified by a circular shift for subsequent pattern. Mudlapur et al. presents a unique RAS cell architecture =-=[31, 32]-=- that aims to minimize the routing complexity. Another novel scan architecture called Progressive Random Access Scan (PRAS) [33] and the associated test application methods have been proposed. It has ...

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...osed. It has a structure similar to static random access memory. Test vector ordering and Hamming distance reduction are proposed to minimize the total number of write operations for a given test set =-=[33, 34]-=-. Partitioned Grid Random Access Scan [35] method uses multiple PRAS grids with partitioning. This method achieves much greater test application time reductions compared to multiple serial scans with ...

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...dom access memory. Test vector ordering and Hamming distance reduction are proposed to minimize the total number of write operations for a given test set [33, 34]. Partitioned Grid Random Access Scan =-=[35]-=- method uses multiple PRAS grids with partitioning. This method achieves much greater test application time reductions compared to multiple serial scans with additional test pins. A test compaction te...

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...utation codes [52], packet-based codes [53] and nonlinear combinational codes [54]. A multi-level Huffman coding scheme that utilizes a LFSR for random filling has been proposed by Kavousianos et al. =-=[55]-=- while Polian et al. [56] proposes use of an evolutionary heuristic with a Huffman code based technique. A scheme based on MICRO (Modified Input reduction and CompRessing One block) code is proposed b...

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... overhead. This technique does not require cyclic scan registers (CSR), which is used by many of the code-based techniques mentioned above that compress the difference of scan vectors. Ruan and Katti =-=[58]-=- presents a data-independent compression method called pattern run-length coding. This compression scheme is a modified run-length coding that encodes consecutive equal/complementary patterns. The sof...

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...cutive equal/complementary patterns. The software-based decompression algorithm is small and requires very few processor instructions. A block merging based compression technique is proposed by Aiman =-=[59]-=- that capitalizes on the fact that many consecutive blocks of the test data can be merged 19stogether. Compression is achieved by storing the merged block and the number of blocks merged. A compressio...

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...tionary with fixed-length indices to generate all distinct output vector [62]. Test-data compression techniques based on LZ77, LZW and test-data realignment methods are proposed by Pomeranz and Reddy =-=[63]-=-, Knieser et al. [64] and Wolff 20sand Papachristou [65], respectively. Li et al. proposed [66] a compression technique using dictionary with fixed-length indices for multiple-scan chain designs. A hy...

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...esults for s38584 for Scan Chain Length of 15 (N=98). . . . . . . . 69 4.13 Results for s38584 for Scan Chain Length of 8 (N=183). . . . . . . . 69 4.14 Comparison with MUXs network based decompressor=-=[90]-=-. . . . . . . . 90 4.15 Comparison with other schemes using the MINTEST dynamic compacted test sets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.16 Comparison with other multiple ...

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...d scheme [90] relies on an iterative test pattern generation 90sTable 4.15: Comparison with other schemes using the MINTEST dynamic compacted test sets. Circuits #TV Proposed [59] [51] [50] [58] [55] =-=[100]-=- [47] [49] [68] s5378 111 4884 10694 10861 10511 9530 9358 11644 11419 11453 11592 s9234 159 5724 19169 16235 17763 15674 15511 17877 21250 20716 18908 s13207 236 19824 24962 26343 24450 18717 18384 3...

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...niques that decrease test data volume and test time are necessary to increase production capacity and reduce test cost. Scan-based test has become very popular in face of increasing design complexity =-=[2]-=- as it offers high level of fault coverage conveniently by using electronic design automation (EDA) tools. Simplicity is a very important feature of scan technology. 1sScan test is easy to understand,...

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...mparison with other multiple scan chain schemes. . . . . . . . . . . 93 4.17 Comparison of H/W costs with two multiple scan chains schemes. . . 94 viiisList of Figures 1.1 Steps in scan-based testing =-=[3]-=-. . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Download of test data to ATE [5]. . . . . . . . . . . . . . . . . . . . . 7 1.3 Conceptual architecture for testing an SoC by storing the encoded te...

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...son of H/W costs with two multiple scan chains schemes. . . 94 viiisList of Figures 1.1 Steps in scan-based testing [3]. . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Download of test data to ATE =-=[5]-=-. . . . . . . . . . . . . . . . . . . . . 7 1.3 Conceptual architecture for testing an SoC by storing the encoded test data (TE) in ATE memory and decoding it using on-chip decoders [?]. 9 3.1 (a) Mul...

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...f techniques have been reported in literature and commercial products from Electronic Design Automation tool vendors are available that integrate test data compression into the overall IC design flow =-=[12, 13]-=-. In order to systematically present the vast number of techniques proposed, they are classified into categories based on the underlying principles. Broadly speaking, the proposed solutions can be cla...

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...e the clock to different scan segments while taking advantage of the regularity and periodicity of scan chains. Another scheme for selective triggering of scan segments was proposed by Sharifi et al. =-=[20]-=-. A novel scheme was presented by Sinanoglu and Orailoglu [21] to reduce test power consumption by freezing scan segments that don’t have care bits in the next test stimulus. By only loading the segme...

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...n of compatibility allows for significant additional compaction leading to gains in data volume reduction. The scan architectures mentioned before are serial. An alternate is Random Access Scan (RAS) =-=[27, 28]-=-. In RAS, flip-flops work as addressable memory elements in the test mode, similar to a random access memory. This approach reduces the time of setting and observing the flip-flop states but requires ...

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...], extended FDR coding [47], MTC coding [48], variable-input Huffman coding (VIHC) coding[49], ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding =-=[51]-=-, mutation codes [52], packet-based codes [53] and nonlinear combinational codes [54]. A multi-level Huffman coding scheme that utilizes a LFSR for random filling has been proposed by Kavousianos et a...

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...ding[49], ninecoded compression technique [50], Burrows-Wheeler transform based compression [?], arithmetic coding [51], mutation codes [52], packet-based codes [53] and nonlinear combinational codes =-=[54]-=-. A multi-level Huffman coding scheme that utilizes a LFSR for random filling has been proposed by Kavousianos et al. [55] while Polian et al. [56] proposes use of an evolutionary heuristic with a Huf...

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...et al. [56] proposes use of an evolutionary heuristic with a Huffman code based technique. A scheme based on MICRO (Modified Input reduction and CompRessing One block) code is proposed by Chun et al. =-=[57]-=- that uses an input reduction technique, test set reordering, and one block compression with a novel mapping scheme to achieve compression with a low area overhead. This technique does not require cyc...

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...test data can be merged 19stogether. Compression is achieved by storing the merged block and the number of blocks merged. A compression scheme using multiple scan chains is proposed by Hayashi et al. =-=[60]-=- based on reduction of distinct scan vectors (words) using selective don’t-care identification. Each bit in the specified scan vectors is fixed to either a 0 or 1, and single/double length coding is u...

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...erconnect based network in approach by Rao et al. [81]. An enhancement of the Illinois Scan Architecture for use with multiple scan inputs is presented by Shah and Patel [82] 22swhile Ashiouei et al. =-=[83]-=- presents a technique for balanced parallel scan to improve ILS technique eliminating the need to scan vectors in serially. In the Scan Chain Concealment approach [77], a pseudorandomly-built XOR netw...

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... fewer conflicts, and more prelude vectors for more conflicts. Therefore, it avoids the extreme solution of serializing all the scan chains to resolve conflicts. 23sIn Selective Low Care (SLC) scheme =-=[87]-=-, the linear dependencies of the internal scan chains are explored, and instead of encoding all the specified bits in test cubes, only a smaller amount of specified bits are selected for encoding. It ...

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...e explored, and instead of encoding all the specified bits in test cubes, only a smaller amount of specified bits are selected for encoding. It employs a Fanout Compression Scan Architecture (FCSCAN) =-=[88]-=-, the basic idea of which is to target the minority specified bits (either a 1 or 0) in scan slices for compression. A compression scheme using reconfigurable linear decompressor has been proposed [89...

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...rence between two original vectors, or the ⌈ N ⌉ subpart of an M N bits original vector. A hybrid scheme that uses horizontal compression combined with dictionary compression is proposed by Li et al. =-=[92]-=- where the output of horizontal compression is further compressed with a dictionary scheme using both fixed and variable length indices. The compression scheme proposed in this work uses the idea of i...