... like Matlab [6] or in languages like C/C++. On the other side tools have been developed in the last decade to describe hardware on a higher abstraction level, the so-called algorithm level, see e.g. =-=[1]-=-, and to automatically map the algorithmic description onto a register-transfer-level-model and finally to a gate-level-implementation of an ASIC- or PLD-library. A commercial tool which implements th...

...lements this so-called “high-level-synthesis” (HLS) or “behavioral synthesis”, see e.g. [2] or [3], is the “CoCentric SystemC Compiler” from Synopsys [10]. It accepts algorithmic descriptions in VHDL =-=[4]-=- or C++/SystemC [5]. According to the constraints given by the designer it tries to find an implementation for the given algorithmic description. In this contribution we will show how HLS can be used ...

...h(2) * h(N-1) of the transposed direct form, as shown in figure 3(b), can be + + + y(n) obtained by applying the trans(a) direct form position theorem to the signal flow graph of the direct form x(n) =-=[9]-=-. A fully parallel hardware implementation of both filter structures requires N multipliers, * h(N-1) * h(N-2) * h(N-3) * h(0) N-1 adders and N-1 registers. T + T + + y(n) Due to the fact, that the di...

...-model and finally to a gate-level-implementation of an ASIC- or PLD-library. A commercial tool which implements this so-called “high-level-synthesis” (HLS) or “behavioral synthesis”, see e.g. [2] or =-=[3]-=-, is the “CoCentric SystemC Compiler” from Synopsys [10]. It accepts algorithmic descriptions in VHDL [4] or C++/SystemC [5]. According to the constraints given by the designer it tries to find an imp...