### Citations

620 |
Digital Integrated Circuits: A Design Perspective, Pearson Education, Upper Saddle River,
- Rabaey, Chandrakasan, et al.
- 2003
(Show Context)
Citation Context ...ir extra carriers, resulting in wider depletion regions and thereby reducing capacitances. Carrier freeze-out also increases the threshold voltage since fewer dopants in the channel are being ionized =-=[24]-=-. The current gain of bipolar devices degrades at low temperatures, reducing the risk of CMOS latchup. Leakage currents are reduced since the reversed bias junction current is directly related to the ... |

566 |
Analysis and Design of Analog Integrated Circuits
- Gray, Meyer
- 1993
(Show Context)
Citation Context ...Cj, and the sidewall capacitance (per unit width), Cjsw. The total capacitance is given by: ( C j ) + ⋅ ( W + L) C jsw C = W ⋅ L ⋅ 2 ⋅ (9) A first order model of this structure is given by two diodes =-=[20]-=-, equivalent to the N+/Pdiodes created by the resistor structure, placed at each end of the resistor. This model is illustrated in Figure 35. The diode model was created from data provided by the IC f... |

521 |
The Design of CMOS Radio-Frequency Integrated Circuits,
- Lee
- 1998
(Show Context)
Citation Context ...It provides both the desired carrier signal, and the source from which data synchronization is derived. The oscillator design solution consists of a simple differential negative resistance oscillator =-=[8]-=-. The differential oscillator topology provides a differential signal input to both the clock divider, and the polyphase filter. The differential oscillator was chosen since this circuit easily provid... |

235 | Phase noise in oscillators: a unifying theory and numerical methods for characterization
- Demir, Mehrotra, et al.
- 2000
(Show Context)
Citation Context ...presents the noise spectrum around the oscillators ideal frequency. Phase errors are characterized by a probability density function of Gaussian distribution with constant mean and diverging variance =-=[32,33]-=-. This distribution can be modeled by a Wiener process. It can be shown that the timing jitter is related to phase noise by [34]: 53 ( dBc/ Hz) Phase_noise / 10 ⎡ ⎤ 2 2 2 2 10 Jitter ( sec ) = Freq _ ... |

143 |
Fundamentals of Microelectronics.
- Razavi
- 2006
(Show Context)
Citation Context ...w, or consume more power than desired. CLK CLK_B MOSFET_NMOS M1 Inv X4 MOSFET_NMOS M2 Figure 17: Dynamic latch divider VDD CLK_B CLK MOSFET_NMOS M3 MOSFET_NMOS M4 The divider illustrated in Figure 17 =-=[16]-=- was investigated for its use as the first divider stage interfacing to the oscillator. The first two inverters operate as dynamic latches controlled by the differential clock input and the final inve... |

123 |
High-speed CMOS circuit technique,”
- Yuan, Svensson
- 1989
(Show Context)
Citation Context ...ck topologies for the main transmitter components Transmitter Circuit Block Design Topology Oscillator Differential Negative Resistance Oscillator Clock Divider SCL and True Single Phase Clock (TSPC) =-=[5,6,7]-=- Mixer Gilbert Cell Double-Balanced Mixer 3.1 Overview The choice of circuit implementation for the main transmitter components yields the detailed block-level transmitter diagram shown in Figure 4. B... |

101 |
The Art of Analog Layout”,
- Hastings
- 2001
(Show Context)
Citation Context ...Figure 73. The two 3 kΩ resistors were split into three sections of 1 kΩ and interdigitated in a common-centroid layout. The common-centroid layout increases the match between the two resistor values =-=[39]-=- assuming that there is a one or two-dimensional change in sheet resistance over distance due to processing variation. This layout strategy only accounts for process variation along orthogonal axes al... |

45 | CMOS mixers and polyphase filters for large image rejection. SolidState Circuits,
- Behbahani, Kishigami, et al.
- 2001
(Show Context)
Citation Context ...k is additionally robust against component mismatches. In order to account for typical process variations, the RC time constants for each stage were varied by ±15% around the 2.4 Ghz design frequency =-=[22, 23]-=-. Cascading three stages has been proven to be highly tolerant to process variations, bounding the gain error to within ±2% [21]. Figure 37 shows a phase error comparison for 1, 2 and 3 stage polyphas... |

35 |
New single-clock CMOS latches and flip flops with improved speed and power savings,‖
- Yuan, Svensson
- 1997
(Show Context)
Citation Context ...ck topologies for the main transmitter components Transmitter Circuit Block Design Topology Oscillator Differential Negative Resistance Oscillator Clock Divider SCL and True Single Phase Clock (TSPC) =-=[5,6,7]-=- Mixer Gilbert Cell Double-Balanced Mixer 3.1 Overview The choice of circuit implementation for the main transmitter components yields the detailed block-level transmitter diagram shown in Figure 4. B... |

23 |
Obtaining the Specific Contact Resistance from Transmission Line Model Measurements,”
- Reeves, Harrison
- 1982
(Show Context)
Citation Context ...be expressed as: ⎛ L ⎞ r = 2 Rc + Rsh⎜ ⎟ ⎝ w ⎠ Equation 5 has a slope, with respect to L, of Rsh/w, with x and y coordinates at Lx and 2Rc, as shown in Figure 104. Furthermore, Rc can be expressed as =-=[40]-=-: Rc = R sk L t w Measured Resistance 2Rc Slope = Rsh/w Pad Spacing, L where Rsk is a modified sheet resistance of the semiconductor material directly under the contact pad. Lt, called the transfer le... |

22 |
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters,
- Floyd
- 2002
(Show Context)
Citation Context ...phase clock and input multiplexers), a gate length of 0.6 μm was feasible and used in the IC layout. 3.2.2.1 SCL Divide-by-Two The first stage of the clock divider was implemented in an SCL flip-flop =-=[10]-=-, shown in Figure 11, connected as a divide-by-two circuit. This configuration used was since differential to single-ended conversion is naturally performed by utilizing the complementary inputs and t... |

15 |
Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks“,
- Huang, Rogenmoser
- 1996
(Show Context)
Citation Context ...ck topologies for the main transmitter components Transmitter Circuit Block Design Topology Oscillator Differential Negative Resistance Oscillator Clock Divider SCL and True Single Phase Clock (TSPC) =-=[5,6,7]-=- Mixer Gilbert Cell Double-Balanced Mixer 3.1 Overview The choice of circuit implementation for the main transmitter components yields the detailed block-level transmitter diagram shown in Figure 4. B... |

14 |
Gallium Arsenide Digital Integrated Circuit Design
- Long, Burner
- 1990
(Show Context)
Citation Context ...ed is increased due to a reduction in the resistivity of metal interconnections. The resistivity of aluminum drops to about one-fifth of its room temperature value (depending on the thickness) at 77K =-=[25, 26]-=-. Despite the above benefits to low temperature operation, the reliability degradation associated with hot-carriers in the channel yields a fundamental concern for our application. Because of the incr... |

14 |
Low-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers
- Weigandt, Low-Phase-Noise
- 1998
(Show Context)
Citation Context ...n of Gaussian distribution with constant mean and diverging variance [32,33]. This distribution can be modeled by a Wiener process. It can be shown that the timing jitter is related to phase noise by =-=[34]-=-: 53 ( dBc/ Hz) Phase_noise / 10 ⎡ ⎤ 2 2 2 2 10 Jitter ( sec ) = Freq _ offset ( Hz ) ⋅ ⎢ 3 ⎥ (11) ⎢⎣ f c ⎥⎦ This relation has been used to evaluate the timing jitter of the transmitter’s oscillator f... |

13 |
A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops
- Chang, Park, et al.
- 1996
(Show Context)
Citation Context ... signal (MDS) [10]. 3.2.2.2 TSPC Divider Chain The remaining divider circuitry was implemented using the TSPC topology. There are many methods and topologies for TSPC flip-flops as frequency dividers =-=[11,12,13]-=-. In deciding the final topology, power dissipation was the main figure of merit. A divide-bytwo block was chosen to follow the SCL divider since higher divide ratios typically involve higher power di... |

9 |
Jitter in Ring Oscillators
- McNeil
- 1997
(Show Context)
Citation Context ...presents the noise spectrum around the oscillators ideal frequency. Phase errors are characterized by a probability density function of Gaussian distribution with constant mean and diverging variance =-=[32,33]-=-. This distribution can be modeled by a Wiener process. It can be shown that the timing jitter is related to phase noise by [34]: 53 ( dBc/ Hz) Phase_noise / 10 ⎡ ⎤ 2 2 2 2 10 Jitter ( sec ) = Freq _ ... |

5 |
The optimization of GHz integrated CMOS quadrature VCO’s based on a poly-phase filter loaded differential oscillator
- Borremans, Muer, et al.
- 2000
(Show Context)
Citation Context ...k is additionally robust against component mismatches. In order to account for typical process variations, the RC time constants for each stage were varied by ±15% around the 2.4 Ghz design frequency =-=[22, 23]-=-. Cascading three stages has been proven to be highly tolerant to process variations, bounding the gain error to within ±2% [21]. Figure 37 shows a phase error comparison for 1, 2 and 3 stage polyphas... |

4 |
A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop.
- Yang, Lee, et al.
- 2001
(Show Context)
Citation Context ... signal (MDS) [10]. 3.2.2.2 TSPC Divider Chain The remaining divider circuitry was implemented using the TSPC topology. There are many methods and topologies for TSPC flip-flops as frequency dividers =-=[11,12,13]-=-. In deciding the final topology, power dissipation was the main figure of merit. A divide-bytwo block was chosen to follow the SCL divider since higher divide ratios typically involve higher power di... |

4 |
Impact of clock slope on true single phase clocked (TSPC) CMOS circuits
- Larsson, Svensson
- 1994
(Show Context)
Citation Context ...tion edge slopes and this output was used in the final design. It is critical for subsequent TSPC stages in the six-phase block (see Section 3.2.2.3) that the transition edges be as sharp as possible =-=[15]-=-. Internal timing problems arise in TSPC building blocks with shallow transition slopes. div_by_2, V div_by_4, V div_by_12, V a 3.0 2.5 2.0 1.5 1.0 4 2 0 -2 4 2 0 -2 PMOS PMOS NMOS b PMOS NMOS NMOS m1... |

4 |
New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures,”
- Wang-Ratkovic, Lacoe, et al.
- 2003
(Show Context)
Citation Context ...ed is increased due to a reduction in the resistivity of metal interconnections. The resistivity of aluminum drops to about one-fifth of its room temperature value (depending on the thickness) at 77K =-=[25, 26]-=-. Despite the above benefits to low temperature operation, the reliability degradation associated with hot-carriers in the channel yields a fundamental concern for our application. Because of the incr... |

3 | Integrated-antenna push-pull power amplifiers
- Deal, Radisic, et al.
- 1999
(Show Context)
Citation Context ...ansmit Antenna Since the transmitter chip features a differential output, a differential antenna stage is required for the wireless interface. 49sFigure 48: Printed dual feed microstrip patch antenna =-=[30]-=- While research into the transmitter and receiver antenna structures is still ongoing, the current design solution currently being pursued is a dual feed microstrip patch antenna [30]. 4. System Synch... |

2 |
Fast CMOS Nonbinary Divider and Counter
- Yuan, Svensson
- 1993
(Show Context)
Citation Context ...t simulation to be approximately 3 Ghz, thus providing an adequate design margin. Port Q_bar MOSFET_PMOS MOSFET13 Length=Lp Width=W_p_inv 3.2.2.2.2 TSPC Divide-by-three The TSPC divide-by-three stage =-=[14]-=- is shown in Figure 14. The divide-by-three stage operates on the same principle as the inverse data-feedback (Qbar to D) flip-flop but incorporates an additional logic function in the feedback path. ... |

2 |
An implementation technique of dynamic CMOS circuit applicable to asynchronous/synchronous logic
- Yoshizawa, Taniguchi, et al.
- 1998
(Show Context)
Citation Context ...of the D input. Table 8: Input functions of the D-Flip-Flop with Synchronous Set D Input Set Input Output HIGH LOW HIGH LOW LOW LOW HIGH HIGH HIGH LOW HIGH HIGH The D-flip-flop with synchronous reset =-=[18]-=- is shown in Figure 31. Referring to Figure 31, with the Reset signal active, the Prechage node is discharged and the Q_bar output is pulled high on a positive clock edge. These two mechanism ensure t... |

2 |
Improved hot-carrier and shortchannel performance in vertical nMOSFETs with graded channel doping
- Chen, Ouyang, et al.
- 1962
(Show Context)
Citation Context ...l resistance and thereby reduces the drivescurrent. Another technique is to grade channel doping by increasing the potential more rapidly near the source end, which reduces the maximum electric field =-=[28]-=-. Hot-carrier degradation typically shifts the threshold voltages such that the digital input low voltage, VIL, and the digital input high voltage, VIH, are increased at low temperatures [29]. The thr... |

2 |
Digital Signal Integrity
- Young
(Show Context)
Citation Context ...input clock feeds all six flip-flops and phase skew between the flip-flops needs to be minimized. To accomplish the necessary clocking phase coherence on all six flip-flops, a Page 1 64s“star-cluster”=-=[38]-=- type of arrangement was used for the 200 MHz clock input. In a starcluster configuration, each flip-flop is connected to the centralized input by equal length interconnect lines. The key design crite... |

1 |
A Short Range Wireless Interface for Cryogenic Imaging Arrays
- Freeman
- 2001
(Show Context)
Citation Context ................... 96 ivsTable of Figures Figure 1: Simplified Quadrature modulator block diagram.............................................. 11 Figure 2: General overview of the communication system =-=[1]-=-......................................... 11 Figure 3: Overview diagram of the QPSK transmitter illustrating the input multiplexing ....................................................................... |

1 |
Double Precharge TSPC for HighSpeed Dual-Modulus
- Chae, Ki, et al.
- 1999
(Show Context)
Citation Context ... signal (MDS) [10]. 3.2.2.2 TSPC Divider Chain The remaining divider circuitry was implemented using the TSPC topology. There are many methods and topologies for TSPC flip-flops as frequency dividers =-=[11,12,13]-=-. In deciding the final topology, power dissipation was the main figure of merit. A divide-bytwo block was chosen to follow the SCL divider since higher divide ratios typically involve higher power di... |

1 |
Design of Analog CMOS Integrated Circuits, pg. 442
- Razavi
- 2001
(Show Context)
Citation Context ...plexer schematic diagram One of the six T-gates is shown in Figure 25. The T-gates were scaled to minimize clock feed-through and charge injection by keeping the transistor widths near minimum values =-=[17]-=-. Table 6 lists the T-gate schematic variables. Port in Implemented as T-gates Port bias_p Port bias_n ph1 ph2 ph3 ph4 ph5 ph6 pwr MOSFET_PMOS MOSFET5 Length=Lp Width=Wp Port out MOSFET_NMOS MOSFET4 L... |

1 |
Single Sideband Modulation Using Sequence Asymmetric Polyphase Networks
- Gingeli
- 1973
(Show Context)
Citation Context ...se of QPSK modulation requires establishing the data channels upon perfectly orthogonal carrier signals. Orthogonality of the differential carrier signals was created using a polyphase filter network =-=[19]-=- as shown in Figure 34. A passive network was chosen to perform the required phase shifting in an effort to conserve power.sDifferential Oscillator Polyphase Filter Figure 34: Polyphase network and on... |

1 |
Ragaie H.F., “On the Design and Sensitivity of RC Sequence Aysmmetric Polyphase Networks
- Galal, Tawfik
(Show Context)
Citation Context ...C C C Iout+ Qout+ IoutQoutFigure 36: One-stage polyphase filter network It can be shown that the voltage transfer function of the quadrature to in-phase output of the single-stage can be expressed as =-=[21]-=-: 39 Diode DIODE1 R R20 R=Rs*(L/W) Diode DIODE2sV V Q I ( j ) ( jω ) ω = jωRC (10) From the above expression it is clear that small mismatches in R or C is highly undesired as changes in either will c... |

1 |
S.,”Gate length scalability of nMOSFETs down to 30 nm: Comparison between LDD and non-LDD structures
- Murakami, Yoshimura, et al.
- 2000
(Show Context)
Citation Context ...om the drain to source through the channel. In order to reduce the electric field in the channel several solutions have been studied. Lightly doped drain (LDD) structure devices have been widely used =-=[25,27]-=- where some of the drain voltage is dropped in the LDD region to reduce the maximum potential. This technique increases channel resistance and thereby reduces the drivescurrent. Another technique is t... |

1 |
Digital Characteristics of CMOS Devices at Cryogenic Temperatures
- Deen
- 1989
(Show Context)
Citation Context ...ic field [28]. Hot-carrier degradation typically shifts the threshold voltages such that the digital input low voltage, VIL, and the digital input high voltage, VIH, are increased at low temperatures =-=[29]-=-. The threshold voltage is more critical in the digital circuitry of the clock divider, six-phase block, and the input multiplexer. To mitigate threshold shifts and device degradation, the gate length... |

1 |
ESD – The Scourge of Electronics
- Hellstrom
- 1998
(Show Context)
Citation Context ...nductors and more shallow doping wells. The basic principle of ESD protection circuits is to protect the component through current limiting resistors and voltage reducing diodes as shown in Figure 61 =-=[37]-=-. 59sIn R R1 Diode D1 Diode D2 Vdd Vss R R2 Figure 61: Simple ESD protection circuit Connection to Main Circuit (Gate,Source,Drain) Resistor R2 is often implemented in an N+ diffusion resistor, creati... |