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...e, increasing the performance of busy-wait locks and barriers is not the only possible rationale for implementing synchronization mechanisms in hardware. Recent work on weaklyconsistent shared memory =-=[1, 13, 28]-=- has suggested the need for synchronization \fences" that provide clean points for memory semantics. Combining networks, likewise, may improve the performance of memory with bursty access patterns (ca...

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...e instructions have uses other than the construction of busy-wait locks. Fetch and store and compare and swap, for example, are essential for manipulating pointers to build concurrent data structures =-=[20, 32]-=-. Because of their general utility, fetch and instructions are substantially more attractive than special-purpose synchronization primitives. Future designs for shared memory machines should include a...

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...ded to be subtle, and costly in time 1sand space, requiring both a large number of shared variables and a large number of operations to coordinate concurrent invocations of synchronization primitives =-=[12, 25,26,36,40]-=-. Modern multiprocessors generally include more sophisticated atomic operations, permitting simpler and faster coordination strategies. Particularly common are various fetch and operations [22], which...

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...d and Kanodia [41], a ticket lock corresponds to the busy-wait implementation of a semaphore using an eventcount and a sequencer. It can also be thought of as an optimization of Lamport's bakery lock =-=[24]-=-, which was designed for fault-tolerance rather than performance. Instead of spinning on the release counter, processors using a bakery lock repeatedly examine the tickets of their peers. Though it pr...

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...IS allocated m shared memory // locally a.cesslble to processor vpld processor private sense Boolean := true processor private vp”ld Integer // a unique virtual processor Index // lnltlally // rounds =-=[1]-=- [k] flag = false for all 1,k // rounds [L] [k] role = // winner If k > 0, I mod z-k = O, 1 + Z-(k–i) < P, and 2-k < P // bye If k > 0, 1 mod 2-k = O, aud 1 + 2- (k-1) >= P // loser lf k > 0 and 1 mod...

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...complexity of the resulting solutions is the principal motivation for the development of fetch and primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=-, but the characteristics of message passing are di erent enough from shared memory operations that solutions do not transfer from one environment tothe other. Our pseudo-code notation is meant to be ...

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...algorithms includes the BBN Butter y [8], the IBM RP3 [37], Cedar [50], the BBN Monarch [42], the NYU Ultracomputer [17], and proposed large-scale multiprocessors with directory-based cache coherence =-=[3]-=-. Our tree-based barrier will also perform well on these machines. It induces less network load, and requires total space proportional to P , rather than P log P , but its critical path is longer by a...

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...roducing delay on each processor between consecutive probes of the lock. The simplest approach employs a constant delay; more elaborate schemes use some sort of backo on unsuccessful probes. Anderson =-=[5]-=- reports the best performance with exponential backo ; our experiments con rm this result. Pseudo-code for a test and set lock with exponential backo appears in algorithm 1. Test and set su ces when u...

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...ded to be subtle, and costly in time 1sand space, requiring both a large number of shared variables and a large number of operations to coordinate concurrent invocations of synchronization primitives =-=[12, 25,26,36,40]-=-. Modern multiprocessors generally include more sophisticated atomic operations, permitting simpler and faster coordination strategies. Particularly common are various fetch and operations [22], which...

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... 14, 38, 49, 511. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network traffic. Pfister and Norton =-=[38]-=- showed that the presence of hot spots can severely degrade performance for all traffic in multistage interconnection networks, not just traffic due to synchronizing processors. As part of a larger st...

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...complexity of the resulting solutions is the principal motivation for the development of fetch and primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=-, but the characteristics of message passing are di erent enough from shared memory operations that solutions do not transfer from one environment tothe other. Our pseudo-code notation is meant to be ...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...complexity of the resulting solutions is the principal motivation for the development of fetch and primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=-, but the characteristics of message passing are di erent enough from shared memory operations that solutions do not transfer from one environment tothe other. Our pseudo-code notation is meant to be ...

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...ended to be subtle, and costly in time and space, requiring both a large number of shared variables and a large number of operations to coordinate concurrent invocations of synchronization primitives =-=[12, 25, 26, 36, 40]-=-. Modern multiprocessors generally include more sophisticated atomic operations, permitting simpler and faster coordination strategies. Particularly common are various fetch and \Phi operations [22], ...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...P; otherwise false // parentpointer = &nodes[floor((i-1)/4)].childnotready[(i-1) mod 4], // or &dummy if i = 0 // childpointers[0] = &nodes[2*i+1].parentsense, or &dummy if 2*i+1 ?= P // childpointers=-=[1]-=- = &nodes[2*i+2].parentsense, or &dummy if 2*i+2 ?= P // initially childnotready = havechild and parentsense = false procedure treebarrier with nodes[vpid] do repeat until childnotready = --false, fal...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...ko , it is not possible to obtain a lock with an expected constant number of network transactions, due to the unpredictability of the length of critical sections. Anderson [5] and Graunke and Thakkar =-=[18]-=-have proposed locking algorithms that achieve the constant bound on cache-coherent multiprocessors that support atomic fetch and increment or fetch and store, respectively. The trick is for each proce...

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...equest counter and waiting until the result (its ticket) is equal to the value of the release counter. It releases the lock by incrementing the release counter. In the terminology of Reed and Kanodia =-=[41]-=-, a ticket lock corresponds to the busy-wait implementation of a semaphore using an eventcount and a sequencer. It can also be thought of as an optimization of Lamport's bakery lock [24], which was de...

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...5,26,36,40]. Modern multiprocessors generally include more sophisticated atomic operations, permitting simpler and faster coordination strategies. Particularly common are various fetch and operations =-=[22]-=-, which atomically read, modify, and write a memory location. Fetch and operations include test and - set, fetch and store (swap), fetch and add, and compare and swap. 1 More recently, there have been...

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...rhead, the test and set lock can be modi ed to use a test and set instruction only when a previous read indicates that the test and set might succeed. This so-called test-and{test and - set technique =-=[44]-=- ensures that waiting processors poll with read requests during the time that a lock is held. Once the lock becomes available, some fraction of the waiting processors detect that the lock is free and ...

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...e shared state variables, and simultaneously eliminate one of the two spinning episodes, by \reversing the sense&quot; of the variables (and leaving them with di erent values) between consecutive barriers =-=[19]-=-. 5 The resulting code is shown in algorithm 7. Arriving processors decrement count and then wait until sense has a di erent value than it did in the previous barrier. The last arriving processor rese...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network traffic. Pfister and Norton [38] showed that...

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...p ag should be the fastest algorithm on large-scale multiprocessors that use broadcast to maintain cache coherence (either in snoopy cache protocols [15] orin directory-based protocols with broadcast =-=[7]-=-). It requires only O(P ) updates to shared variables in order to tally arrivals, compared to O(P log P ) for the dissemination barrier. Its updates are simple writes, which are cheaper than the read-...

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...complexity of the resulting solutions is the principal motivation for the development of fetch and primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=-, but the characteristics of message passing are di erent enough from shared memory operations that solutions do not transfer from one environment tothe other. Our pseudo-code notation is meant to be ...

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...lier are not running. In this situation the test and set lock may be preferred to the FIFO alternatives. Additional mechanisms can ensure that a process is not preempted while actually holding a lock =-=[47, 52]-=-. All of the spin lock algorithms wehave considered require some sort of fetch and instructions. The test and set lock of course requires test and set. The ticket lock requires fetch and - increment. ...

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...complexity of the resulting solutions is the principal motivation for the development of fetch and primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=-, but the characteristics of message passing are di erent enough from shared memory operations that solutions do not transfer from one environment tothe other. Our pseudo-code notation is meant to be ...

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...e CPU resources if spinning processes may be preempted. (Busy-wait barriers may also waste cycles in the presence of preemption.) We can avoid this problem by co-scheduling processes that share locks =-=[34]-=-. Alternatively (for mutual exclusion), a test and set lock with exponential backo will allow latecomers to acquire the lock when processes that arrived earlier are not running. In this situation the ...

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... algorithm uses no atomic instructions other than read and write, and performs the minimum possible number of operations across the processor-memory interconnect. 3.3 The Dissemination Barrier Brooks =-=[9]-=- has proposed a symmetric \butter y barrier,&quot; in which processors participate as equals, performing the same operations at each step. Each processor in a butter y barrier participates in a sequence of...

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... and store (swap), fetch and add, and compare and swap. 1 More recently, there have been proposals for multistage interconnection networks that combine concurrent accesses to the same memory location =-=[17, 37, 42]-=-, multistage networks that have special synchronization variables embedded in each stage of the network [21], and special-purpose cache hardware to maintain a queue of processors waiting for the same ...

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... and store (swap), fetch and add, and compare and swap. 1 More recently, there have been proposals for multistage interconnection networks that combine concurrent accesses to the same memory location =-=[17, 37, 42]-=-, multistage networks that have special synchronization variables embedded in each stage of the network [21], and special-purpose cache hardware to maintain a queue of processors waiting for the same ...

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...lier are not running. In this situation the test and set lock may be preferred to the FIFO alternatives. Additional mechanisms can ensure that a process is not preempted while actually holding a lock =-=[47, 52]-=-. All of the spin lock algorithms wehave considered require some sort of fetch and instructions. The test and set lock of course requires test and set. The ticket lock requires fetch and - increment. ...

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...sor resets count and reverses sense. Consecutive barriers cannot interfere with each other because all operations on count occur before sense is toggled to release the waiting processors. Lubachevsky =-=[29]-=- presents a similar barrier algorithm that uses two shared counters and a processor private two-state flag. The private flag selects which counter to use; consecutive barriers use alternate counters. ...

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...well to large numbers of processors, even using adaptive backo strategies. Our experiments (see section 4.4) con rm this conclusion. 6 Commenting on Tang and Yew's barrier algorithm (algorithm 3.1 in =-=[48]-=-), Agarwal and Cherian [2] show that on a machine in which contention causes memory accesses to be aborted and retried, the expected number of memory accesses initiated by each processor to achieve a ...

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...tistage networks that have special synchronization variables embedded in each stage of the network [21], and special-purpose cache hardware to maintain a queue of processors waiting for the same lock =-=[14, 28,35]-=-. The principal purpose of these hardware primitives is to reduce the impact of busy waiting. Before adopting them, it is worth considering the extent to which software techniques can achieve a simila...

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... and store (swap), fetch and add, and compare and swap. 1 More recently, there have been proposals for multistage interconnection networks that combine concurrent accesses to the same memory location =-=[17, 37, 42]-=-, multistage networks that have special synchronization variables embedded in each stage of the network [21], and special-purpose cache hardware to maintain a queue of processors waiting for the same ...

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...ded to be subtle, and costly in time 1sand space, requiring both a large number of shared variables and a large number of operations to coordinate concurrent invocations of synchronization primitives =-=[12, 25,26,36,40]-=-. Modern multiprocessors generally include more sophisticated atomic operations, permitting simpler and faster coordination strategies. Particularly common are various fetch and operations [22], which...

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...ded to be subtle, and costly in time 1sand space, requiring both a large number of shared variables and a large number of operations to coordinate concurrent invocations of synchronization primitives =-=[12, 25,26,36,40]-=-. Modern multiprocessors generally include more sophisticated atomic operations, permitting simpler and faster coordination strategies. Particularly common are various fetch and operations [22], which...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...nodes array would be scattered statically across the memory banks of the machine, or replaced by a scattered set of variables. 3.4 Tournament Barriers Hensgen, Finkel, and Manber [19] and Lubachevsky =-=[30]-=- have also devised tree-style \tournament&quot; barriers. The processors involved in a tournament barrier begin at the leaves of a binary tree, much as they would in a combining tree of fan-in two. One pro...

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...t of an idle machine) on the Butter y caused by 60 processor barriers using local and network polling strategies. 35 4 4 4 4 4 4 4 4 4sindependent of the network topology. A study by Kumar and P ster =-=[23]-=- shows the onset of hot-spot contention to be rapid. P ster and Norton argue for hardware message combining in interconnection networks to reduce the impact of hot spots. They base their argument prim...

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...ut using the interconnection network. On a machine with coherent caches, processors spin only on locations in their caches. On a machine in which shared memory is distributed (e.g., the BBN Butterfly =-=[8]-=-, the IBM RP3 [37], or a shared-memory hypercube [10]), processors spin only on locations in the local portion of shared memory. The implication of our work is that efficient synchronization algorithm...

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...by a constant factor), and is therefore faster. The class of machines for which the dissemination barrier should outperform all other algorithms includes the BBN Butter y [8], the IBM RP3 [37], Cedar =-=[50]-=-, the BBN Monarch [42], the NYU Ultracomputer [17], and proposed large-scale multiprocessors with directory-based cache coherence [3]. Our tree-based barrier will also perform well on these machines. ...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...terconnection networks that combine concurrent accesses to the same memory location [17, 37, 42], multistage networks that have special synchronization variables embedded in each stage of the network =-=[21]-=-, and special-purpose cache hardware to maintain a queue of processors waiting for the same lock [14, 28,35]. The principal purpose of these hardware primitives is to reduce the impact of busy waiting...

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...e instructions have uses other than the construction of busy-wait locks. Fetch and store and compare and swap, for example, are essential for manipulating pointers to build concurrent data structures =-=[20, 32]-=-. Because of their general utility, fetch and \Phi instructions are substantially more attractive than special-purpose synchronization primitives. Future designs for shared memory machines should incl...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...with coherent caches, processors spin only on locations in their caches. On a machine in which shared memory is distributed (e.g., the BBN Butter y [8], the IBM RP3 [37], or a shared-memory hypercube =-=[10]-=-), processors spin only on locations in the local portion of shared memory. The implication of our work is that e cient synchronization algorithms can be constructed in software for shared-memory mult...

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...and_store (swap) , fetch-and-add, and compare _and_swap.1 More recently, there have been proposals for multistage interconnection networks that combine concurrent accesses to the same memory location =-=[17, 37, 42]-=-, multistage networks that have special synchronization variables embedded in each stage of the network [211, and special-purpose cache hardware to maintain a queue of processors waiting for the same ...

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...kel, and Manber's algorithm to use sense reversal to avoid re-initializing ag variables in each round. These same modi cations have been discovered independently by Craig Lee of Aerospace Corporation =-=[27]-=-. Hensgen, Finkel, and Manber provide performance gures for the Sequent Balance (a bus-based, cache-coherent multiprocessor), comparing their tournament algorithm against the dissemination barrier, as...

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...P; otherwise false // parentpointer = &nodes[floor((i-1)/4)].childnotready[(i-1) mod 4], // or &dummy if i = 0 // childpointers[0] = &nodes[2*i+1].parentsense, or &dummy if 2*i+1 >= P // childpointers=-=[1]-=- = &nodes[2*i+2].parentsense, or &dummy if 2*i+2 >= P // initially childnotready = havechild and parentsense = false procedure tree_barrier with nodes[vpid] do repeat until childnotready = {false, fal...

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... and store (swap), fetch and add, and compare and swap. 1 More recently, there have been proposals for multistage interconnection networks that combine concurrent accesses to the same memory location =-=[17, 37, 42]-=-, multistage networks that have special synchronization variables embedded in each stage of the network [21], and special-purpose cache hardware to maintain a queue of processors waiting for the same ...

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...e bottlenecks that become markedly more pronounced in larger machines and applications. As a consequence, the overhead of busy-wait synchronization is widely regarded as a serious performance problem =-=[2, 6, 11, 14, 38, 49, 51]-=-. When many processors busy-wait on a single synchronization variable, they create a hot spot that is the target of a disproportionate share of the network tra c. P ster and Norton [38] showed that th...

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...out using the interconnection network. On a machine with coherent caches, processors spin only on locations in their caches. On a machine in which shared memory is distributed (e.g., the BBN Butter y =-=[8]-=-, the IBM RP3 [37], or a shared-memory hypercube [10]), processors spin only on locations in the local portion of shared memory. The implication of our work is that e cient synchronization algorithms ...

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... algorithm uses no atomic instructions other than read and write, and performs the minimum possible number of oprations across the processor-memory interconnect. 3.3. The Dissemination Barrier Brooks =-=[9]-=- has proposed a symmetric “butterfly barrier,” in which processors participate as equals, performing the same operations at each step. Each processor in a butterfly barrier participates in a sequence ...

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...and_store (swap) , fetch-and-add, and compare _and_swap.1 More recently, there have been proposals for multistage interconnection networks that combine concurrent accesses to the same memory location =-=[17, 37, 42]-=-, multistage networks that have special synchronization variables embedded in each stage of the network [211, and special-purpose cache hardware to maintain a queue of processors waiting for the same ...

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...e contention due to synchronization|is invalid. 14 P ster and Norton estimate that message combining will increase the size and possibly the cost of an interconnection network 6- to 32-fold. Gottlieb =-=[16]-=- indicates that combining networks are di cult to bit-slice. 36s5 Summary of Recommendations We have presented a detailed comparison of new and existing algorithms for busy-wait synchronization on sha...

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...ded to be subtle, and costly in time 1sand space, requiring both a large number of shared variables and a large number of operations to coordinate concurrent invocations of synchronization primitives =-=[12, 25,26,36,40]-=-. Modern multiprocessors generally include more sophisticated atomic operations, permitting simpler and faster coordination strategies. Particularly common are various fetch and operations [22], which...

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...equest counter and waiting until the result (its ticket) is equal to the value of the release counter. It releases the lock by incrementing the release counter. In the terminology of Reed and Kanodia =-=[41]-=-, a ticket lock corresponds to the busy-wait implementation of a semaphore using an eventcount and a sequencer. It can also be thought of as an optimization of a Lamport’s bakery lock [241, which was ...

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...sor resets count and reverses sense. Consecutive barriers cannot interfere with each other because all operations on count occur before sense is toggled to release the waiting processors. Lubachevsky =-=[29]-=- presents a similar barrier algorithm that uses two shared counters and a processor private two-state ag. The private ag selects which counter to use; consecutive barriers use alternate counters. Anot...

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...o be a problem. Our tree-based barrier with wakeup flag should be the fastest algorithm on large-scale multiprocessors that use broadcast to maintain cache coherence (either in snoopy cache protocols =-=[15]-=- or in directory-based protocols with broadcast [71). It requires only 0(P) updates to shared variables in order to tally arrivals compared to 0( P log P) for the dissemination barrier. Its updates ar...

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...instructions have uses other than the construction of busy-wait locks. Fetch_ and_store and compare_ and_swap, for example, are essential for manipulating pointers to build concurrent data structures =-=[20, 32]-=-. Because of their general utility, f et ch_and_@ instructions are substantially more attractive than special-purpose synchronization primitives. Future designs for shared memory machines should inclu...

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...l, and Manber’s algorithm to use sense reversal to avoid reinitializing flag variables in each round. These same modifications have been discovered independently by Craig Lee of Aerospace Corporation =-=[27]-=-. Hensgen, Finkel, and Manber provide performance figures for the Sequent Balance (a bus-based, cache-coherent multiprocessor), comparing their tournament algorithm against the dissemination barrier a...

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...plexity of the resulting solutions is the principal motivation for the development of fetch_ and_@ primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=- but the ‘Hardware combmmg can reduce the time to achieve a barrier from ()(log P) to O(1) steps If processors happen to arrive at the barrier simultaneously ACM Transactions on Computer Systems, Vol ...

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...plexity of the resulting solutions is the principal motivation for the development of fetch_ and_@ primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=- but the ‘Hardware combmmg can reduce the time to achieve a barrier from ()(log P) to O(1) steps If processors happen to arrive at the barrier simultaneously ACM Transactions on Computer Systems, Vol ...

Citation Context

...plexity of the resulting solutions is the principal motivation for the development of fetch_ and_@ primitives. Other researchers have considered mutual exclusion in the context of distributed systems =-=[31, 39, 43, 45, 46]-=- but the ‘Hardware combmmg can reduce the time to achieve a barrier from ()(log P) to O(1) steps If processors happen to arrive at the barrier simultaneously ACM Transactions on Computer Systems, Vol ...