Efficiently Supporting Fault-Tolerance in FPGAs

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Efficiently Supporting Fault-Tolerance in FPGAs (1998)

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by John Lach

Venue:	Proc. ACM International Symp. on Field-Programmable Gate Arrays
Citations:	16 - 0 self

Citations

375	Digital Systems Testing and Testable Design - Abramovici, Breuer, et al. - 1994 (Show Context) Citation Context ...2 Fault Model, Testing and Diagnosis The proposed approach requires fault detection and a diagnosis method as a preprocessing step. We assume a widely used single stuck at, open, or short fault model =-=[1]-=-. It is interesting to note that our strategy actually covers many simultaneous faults as long as each tile (see Sections 5 and 6) has at most one faulty CLB. In its current form, our approach does no...
177	Reliable Computer Systems Design and Evaluation. - Siewiorek, Swarz - 1992 (Show Context) Citation Context ...sion launched in 1996 by NASA relies on Actel FPGAs for some system services.sUnlike early applications, these high volume and mission critical systems tend to have stringent reliability requirements =-=[19]-=-.sThus, there is a drive from the user community to improve reliability through some level of fault-tolerance. Unfortunately, current technology trends tend to make FPGAs less reliable.sFPGA vendors h...
151	Architecture of field-programmable gate arrays,” - Rose, Gamal, et al. - 1993 (Show Context) Citation Context ...owing three lines of research: FPGA synthesis, fault-tolerant design, and FPGA yield enhancement. A number of different FPGA architectures and synthesis techniques have been proposed and demonstrated =-=[16, 2]-=-. Conceptually, our fault-tolerance approach is closest to BISR techniques.sThe main targets for BISR are systems that are bit-, byte-, or digit- sliced. These types of systems include SRAM and DRAM m...
102	The Programmable Logic Data Book, - Xilinx - 1993 (Show Context) Citation Context ...agnosis steps of the approach. 3.1 FPGA Architecture Model The new fault-tolerance approach is demonstrated using the Xilinx XC4000EX family as the target architecture, specifically the XC4028EXBG352 =-=[24]-=-.sHowever, neither the general concept nor the optimization algorithms are specific to the 4000EX family, or even Xilinx architectures. Any FPGA architecture supporting the ability to reconfigure a la...
31	An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays - Huang, Lombardi - 1996 (Show Context) Citation Context ...been developed for detecting faults in FPGAs through exhaustive testing of the device architecture.sMost of these approaches can be classified as off-line.sFor example, with Built-In Self-Test (BIST) =-=[13, 21, 8, 3]-=-, the FPGA is loaded with a small testing circuit that is restricted to a specific physical region of the device, which is then used to test another portion of the device. The test circuit is moved ac...
29	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead - Stroud, Konala, et al. - 1996 (Show Context) Citation Context ...been developed for detecting faults in FPGAs through exhaustive testing of the device architecture.sMost of these approaches can be classified as off-line.sFor example, with Built-In Self-Test (BIST) =-=[13, 21, 8, 3]-=-, the FPGA is loaded with a small testing circuit that is restricted to a specific physical region of the device, which is then used to test another portion of the device. The test circuit is moved ac...
24	The yield enhancement of field-programmable gate arrays. - Howard, Tyrrell, et al. - 1994 (Show Context) Citation Context ...ical point of view, are programmable logic arrays PLAs [4, 10, 23, 6].sA simple, yet powerful methodology for the implementation of ALU byte slices was proposed by Levitt et. al. [11]. Howard et. al. =-=[7]-=- and Dutt et. al. [5] have proposed using similar regularly structured BISR techniques for improving FPGA yield.sSpare resources are allocated, and a manufacturing step is used to swap spare CLBs for ...
19	Configuration of VLSI Arrays in the Presence of Defects", - Greene, Gamal - 1984 (Show Context) Citation Context ... essentially all modern DRAM designs.sAmong other BISR bit-sliced devices, the most popular and well addressed, from both a theoretical and practical point of view, are programmable logic arrays PLAs =-=[4, 10, 23, 6]-=-.sA simple, yet powerful methodology for the implementation of ALU byte slices was proposed by Levitt et. al. [11]. Howard et. al. [7] and Dutt et. al. [5] have proposed using similar regularly struct...
15	A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield - Moore - 1986 (Show Context) Citation Context ...tually, our fault-tolerance approach is closest to BISR techniques.sThe main targets for BISR are systems that are bit-, byte-, or digit- sliced. These types of systems include SRAM and DRAM memories =-=[14]-=-, as well as systems designed using a set of bit planes and arithmeticlogic units (ALUs), assembled from ALU byte slices [19]. By far the most important use of bit-sliced BISR is in SRAM and DRAM circ...
13	A new statistical approach for fault-tolerant VLSI systems - Stapper - 1992 (Show Context) Citation Context ...stop functioning in response to rare sequences of inputs (e.g. due to a power density surge in a small part of the design).sFor this type of model, we follow the gammadistribution Stapper fault model =-=[20]-=-. The model is applicable on any integrated circuit with regular repetitive structure, including memories and FPGA devices. In the remainder of the section, we elaborate on technical details related t...
12	A user programmable reconfigurable logic array - Carter - 1986 (Show Context) Citation Context ...owing three lines of research: FPGA synthesis, fault-tolerant design, and FPGA yield enhancement. A number of different FPGA architectures and synthesis techniques have been proposed and demonstrated =-=[16, 2]-=-. Conceptually, our fault-tolerance approach is closest to BISR techniques.sThe main targets for BISR are systems that are bit-, byte-, or digit- sliced. These types of systems include SRAM and DRAM m...
9	Node-Covering Based Defect and Fault-Tolerance methods for Increased Yield in FPGAs - Hanchek, Dutt - 1995 (Show Context) Citation Context ...re programmable logic arrays PLAs [4, 10, 23, 6].sA simple, yet powerful methodology for the implementation of ALU byte slices was proposed by Levitt et. al. [11]. Howard et. al. [7] and Dutt et. al. =-=[5]-=- have proposed using similar regularly structured BISR techniques for improving FPGA yield.sSpare resources are allocated, and a manufacturing step is used to swap spare CLBs for faulty components.sAl...
9	Fault-Tolerant Semiconductor Memories - Sarrazin, Malek - 1984 (Show Context) Citation Context ...well as systems designed using a set of bit planes and arithmeticlogic units (ALUs), assembled from ALU byte slices [19]. By far the most important use of bit-sliced BISR is in SRAM and DRAM circuits =-=[17, 9, 22]-=-. The bit-sliced BISR in memories significantly increases memory production profitability and is regularly used in essentially all modern DRAM designs.sAmong other BISR bit-sliced devices, the most po...
7	A RowBased FPGA for Single and Multiple Stuck-At Fault Detection - Chen, Huang, et al. - 1995 (Show Context) Citation Context ...been developed for detecting faults in FPGAs through exhaustive testing of the device architecture.sMost of these approaches can be classified as off-line.sFor example, with Built-In Self-Test (BIST) =-=[13, 21, 8, 3]-=-, the FPGA is loaded with a small testing circuit that is restricted to a specific physical region of the device, which is then used to test another portion of the device. The test circuit is moved ac...
5	Fault Covers in Reconfigurable PLA's - Hassan, Liu - 1990 (Show Context) Citation Context ... essentially all modern DRAM designs.sAmong other BISR bit-sliced devices, the most popular and well addressed, from both a theoretical and practical point of view, are programmable logic arrays PLAs =-=[4, 10, 23, 6]-=-.sA simple, yet powerful methodology for the implementation of ALU byte slices was proposed by Levitt et. al. [11]. Howard et. al. [7] and Dutt et. al. [5] have proposed using similar regularly struct...
4	Optimized Redundancy Selection Based on Failure-Related Yield Model for 64-Mb DRAM and Beyond - Kikuda, Miyamoto, et al. - 1991 (Show Context) Citation Context ...well as systems designed using a set of bit planes and arithmeticlogic units (ALUs), assembled from ALU byte slices [19]. By far the most important use of bit-sliced BISR is in SRAM and DRAM circuits =-=[17, 9, 22]-=-. The bit-sliced BISR in memories significantly increases memory production profitability and is regularly used in essentially all modern DRAM designs.sAmong other BISR bit-sliced devices, the most po...
4	Timing Driven Placement Reconfiguration for Fault-Tolerance and Yield Enhancement in FPGAs - Mathur, Liu - 1996 (Show Context) Citation Context ...ong with on-chip fuses, to increase production yield on the 10K parts. Mathur and Liu have proposed using modified place-androute tools to reroute part of the net-list in the vicinity of a faulty CLB =-=[12]-=-. Our approach is completely transparent to the existing CAD tool chain and exists as an intermediate step that is used in conjunction with existing synthesis and place-and-route tools.sUnlike the BIS...
4	A 30-ns 64-Mb DRAM with Builtin-Self-Test and Self-Repair Functions - al - 1992
3	A 30-ns 64-Mb DRAM with Built-in Self-Test and Self-Repair Function - Tanabe - 1992 (Show Context) Citation Context ...well as systems designed using a set of bit planes and arithmeticlogic units (ALUs), assembled from ALU byte slices [19]. By far the most important use of bit-sliced BISR is in SRAM and DRAM circuits =-=[17, 9, 22]-=-. The bit-sliced BISR in memories significantly increases memory production profitability and is regularly used in essentially all modern DRAM designs.sAmong other BISR bit-sliced devices, the most po...
2	Digital Systems Testing and Testable Designs - al - 1990
2	Architectures of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency - al - 1990
2	Fault Scanner for Reconfigurable Logic - Shnidman, Mangione-Smith, et al. - 1997 (Show Context) Citation Context ...off-line approach. Recently, an on-line testing scheme has been developed for bus-based FPGAs that avoids these problems and may be well suited for fault-detection within this faulttolerance approach =-=[18]-=-. 4. Related Work Related work can be traced along the following three lines of research: FPGA synthesis, fault-tolerant design, and FPGA yield enhancement. A number of different FPGA architectures an...
2	A Test Methodology for Configurable Logic Blocks of a Look-up Table Based FPGA - Michinishi - 1996 (Show Context) Citation Context ...been developed for detecting faults in FPGAs through exhaustive testing of the device architecture.sMost of these approaches can be classified as off-line.sFor example, with Built-In Self-Test (BIST) =-=[13, 21, 8, 3]-=-, the FPGA is loaded with a small testing circuit that is restricted to a specific physical region of the device, which is then used to test another portion of the device. The test circuit is moved ac...
1	A User Programmable Reconfigurable Logic Array - al - 1986
1	A Row-Based FPGA for Single Multiple Stuck-At Fault Detection - al - 1995
1	The Yield Enhancement of Field-Programmable Gate Arrays - al - 1994
1	Introducing Redundancy into VLSI Designs for Yield and - Koren, Pradhan - 1985 (Show Context) Citation Context ... essentially all modern DRAM designs.sAmong other BISR bit-sliced devices, the most popular and well addressed, from both a theoretical and practical point of view, are programmable logic arrays PLAs =-=[4, 10, 23, 6]-=-.sA simple, yet powerful methodology for the implementation of ALU byte slices was proposed by Levitt et. al. [11]. Howard et. al. [7] and Dutt et. al. [5] have proposed using similar regularly struct...
1	A Study of the Data Communication Problems - al - 1968
1	A Test Methodology for Configurable Logic Blocks of a Look-up Table Based FPGA - al - 1996
1	Testing for Cosmic SoftError Rate - “Field - 1996
1	Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch - al - 1996
1	On the Design of a Redundant Programmable Logic Array (RPLA - al - 1987
1	A Study of the Data Communication Problems - Levitt - 1968 (Show Context) Citation Context ...theoretical and practical point of view, are programmable logic arrays PLAs [4, 10, 23, 6].sA simple, yet powerful methodology for the implementation of ALU byte slices was proposed by Levitt et. al. =-=[11]-=-. Howard et. al. [7] and Dutt et. al. [5] have proposed using similar regularly structured BISR techniques for improving FPGA yield.sSpare resources are allocated, and a manufacturing step is used to ...
1	Testing for Cosmic SoftError Rate - O’Gorman - 1996 (Show Context) Citation Context ...iations by a factor higher than 200 are not uncommon [25].sExperiments indicate that in FPGA-like devices at an altitude of 20 km, error rates significantly higher than once per 1000 hours are common =-=[15]-=-.sAlso, as circuit devices become smaller, they become more sensitive to soft faults [25]. If one considers the multiyear life of computing devices and other sources of potential errors (e.g. power su...
1	On the Design of a Redundant Programmable Logic Array (RPLA - Wey - 1987 (Show Context) Citation Context ... essentially all modern DRAM designs.sAmong other BISR bit-sliced devices, the most popular and well addressed, from both a theoretical and practical point of view, are programmable logic arrays PLAs =-=[4, 10, 23, 6]-=-.sA simple, yet powerful methodology for the implementation of ALU byte slices was proposed by Levitt et. al. [11]. Howard et. al. [7] and Dutt et. al. [5] have proposed using similar regularly struct...