Alexander V. Veidenbaum, Qingbo Zhao, Abduhl Shameer  Home/Search
Context Related
| uci.edu/pub/alexv/Paper...IJHSC99.ps.gz uci.edu/~alexv/Papers/IJHSC99.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: uci.edu/~alexv/pubs99 (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: This paper presents a novel instruction cache prefetching mechanism for multiple-issue processors. Such processors at high clock rates often have to use a small instruction cache which can have significant miss rates. Prefetching from secondary cache or even memory can hide the instruction cache miss penalties, but only if initiated sufficiently far ahead of the current program counter. Existing instruction cache prefetching methods are strictly sequential and do not prefetch past conditional... (Update)
Context of citations to this paper: More
.... Instruction cache prefetching has been shown to be an effective technique for improving instruction fetch performance [2, 9, 6, 7, 13, 17, 18, 20, 21], and this is the focus of our paper. We recently proposed a scalable fetch architecture to relieve the fetch bottleneck...
...Moreover, these techniques do not attempt to cover miss penalties associated with taken branches. The non sequential techniques [4, 12, 15, 17] are closely tied to branch prediction. The objective of these techniques is to predict the addresses of instructions that will be...
Cited by: More
Branch History Guided Instruction Prefetching - Srinivasan, Davidson, Tyson.. (2001) (Correct)
Fetch Directed Instruction Prefetching - Reinman, Calder, Austin (1999) (Correct)
Similar documents (at the sentence level):
55.5%: Instruction Cache Prefetching Using Multilevel Branch Prediction - Veidenbaum (1997) (Correct)
Active bibliography (related documents): More All
0.5: Hardware Based Prefetching Methods - Ebenezer (1998) (Correct)
0.3: Multiple Branch Prediction for Wide-Issue Superscalar - Shu-Lin Hwang Che-Chun (Correct)
0.2: Design of Trace Caches for High Bandwidth Instruction Fetching - Sung (Correct)
Similar documents based on text: More All
0.3: Execution History Guided Instruction Prefetching - Zhang, Haga, Barua (2002) (Correct)
0.1: The Effect of Limited Network Bandwidth and its Utilization.. - Kim, Veidenbaum (Correct)
0.1: On Shortest Path Routing in Single Stage Shuffle-Exchange.. - Kim, Veidenbaum (1995) (Correct)
Related documents from co-citation: More All
2: Instruction Prefetching Using Branch Prediction Information (context) - Chen, C-C et al. - 1997
2: Cooperative prefetching: Compiler and hardware support for effective instruction.. - Luk, Mowry - 1998
BibTeX entry: (Update)
A. Veidenbaum, Q. Zhao, and A. Shameer. Non-sequential instruction cache prefetching for multiple-issue processors. International Journal of High-Speed Computing, 10(1):115--140, 1999. http://citeseer.ist.psu.edu/veidenbaum99nonsequential.html More
@article{ veidenbaum99nonsequential,
author = "A. V. Veidenbaum and Q. Zhao and A. Shameer",
title = "Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors",
journal = "International Journal of High Speed Computing (IJHSC)",
volume = "10",
number = "1",
pages = "115--??",
year = "1999",
url = "citeseer.ist.psu.edu/veidenbaum99nonsequential.html" }
Citations (may not include all citations):443 Improving direct-mapped cache performance by the addition of.. - Jouppi - 1990
241 A Study of Branch Prediction Strategies (context) - Smith - 1981
214 Combining Branch Predictors - McFarling - 1993
185 Branch prediction strategies and branch-target buffer design (context) - Smith, Lee - 1984
183 Trace Cache: a Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Bennett et al. - 1996
115 Program Optimization for Instruction Caches (context) - McFarling - 1992
110 Improving the Accuracy of Dynamic Branch Prediction Using Br.. (context) - Pan, So et al. - 1992
107 Achieving High Instruction Cache Performance with an Optimiz.. (context) - Hwu, Chang - 1989
104 Prefetching using Markov Predictors - Joseph, Grunwald - 1997
93 Optimization of Instruction Fetch Mechanism for High Issue R.. - Conte, Menezes et al. - 1995
91 Two Level Adaptive Branch Prediction (context) - Yeh, Patt - 1991
75 Increasing Instruction Fetch Rate via Multiple Branch Predic.. - Yeh, Marr et al. - 1993
64 Missing the Memory Wall: the Case for Processor/Memory Integ.. (context) - Saulsbury, Pong et al. - 1996
63 Trade-offs in Two-level On-chip caching - Jouppi, Wilton - 1994
57 Using Hybrid Branch predictors to Improve Branch Prediction .. - Evers, Chang et al. - 1996
52 Instruction Fetching: Coping with Code Bloat (context) - Uhlig, Nagle et al. - 1995
47 Correlation and Aliasing in Dynamic Branch Prediction (context) - Sechrest, Lee et al. - 1996
36 Control Flow Prediction with Tree-Like Subgraphs for Supersc.. (context) - Dutta, Franklin - 1995
35 Computer Architecture, a Quantative Approach (context) - Hennessy, Patterson - 1996
34 Prefetching in Supercomputer Instruction Caches (context) - Smith, Hsu - 1992
30 Alternative Implementations of Hybrid Branch Predictors - Chang, Hao et al. - 1995
29 Next Cache Line and Set Prediction - Calder, Grunwald - 1995
16 Superscalar Instruction Execution in the 21164 Alpha Micropr.. (context) - Edmondson, Rubinfeld et al. - 1995
15 An effective on-chip preloading scheme to reduce data access.. (context) - Baer, Chen - 1991
14 Instruction Cache Fetch Policies for Speculative Execution - Lee, Baer et al. - 1995
13 Engineering a RISC Compiler System (context) - Chow, Himelstein et al. - 1986
7 Path Prediction for High Issue-Rate Processors - Menezes, Sathaye et al. - 1997
3 Multiple-Block Ahead Branch Prediction (context) - Seznec, Jourdan et al. - 1996
2 Digital Equipment Coporation (context) - Handbook - 1982
2 Instruction Prefetching of Systems Codes with Optimized Layo.. (context) - Xia, Torrrellas - 1996
2 Performance evaluation of instruciton prefetching using mult.. (context) - Zhao - 1996
2 Pentium Processor Data Book (context) - User's, Vol - 1993
2 Instruction Cache Prefetching using Multilevel Branch Predic.. - Veidenbaum - 1997
1 Multi-level Branch Target Buffer for Prefetching Across Bran.. (context) - Shameer - 1998
Documents on the same site (http://www.ics.uci.edu/~alexv/pubs99.html): More
An Integrated Hardware/Software Data Prefetching Scheme for .. - Gornish, Veidenbaum (1994) (Correct)
Interconnection Network Organization and Its Impact on.. - Kim, Veidenbaum (Correct)
Second-level Cache Organization for Data Prefetching - Kim, Veidenbaum (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC