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by Alexis Vartanian, Jean-luc Bechennec, Nathalie Drach-temam
In Proceedings of the 6th International Symposium on High Performance Computer Architecture
http://www.lri.fr/~alex/publis/paper0799.ps.gz
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Abstract:
The quality of a real-time high end virtual reality system depends on its ability to draw millions of textured triangles in 1/60s. The idea of using commodity PC 3D accelerators to build a parallel machine instead of custom ASICs seems more and more attractive as such chips are getting faster. If image parallelism is used, designers have the choice between two distributions: line interleaving and square block interleaving. Having fixed block shape and size makes chip design easier. A PC 3D accelerator has a cost-effective external bus and an on-chip texture cache. The performance of such a cache depends on spatial locality. If the image is rendered in multiple engines, this locality is reduced. Locality and load balancing depend on the distribution scheme of the machine. This paper investigates the impact of the distribution scheme on the performance of such a machine. We use detailed cache and memory system simulations with virtual reality benchmarks running on different configurations. We show that: (i) Both distributions have the same maximum performance with less than 16 processors but square block has a better speedup with 64 processors. (ii) SLI best block size depends on the number of processors of the machine and is not suitable for a scalable chip with a fixed block size. (iii) Using a big triangle buffer in the texture mapping engine has a very important impact on the performance. 1
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