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  Mixed control/data-flow representation for modelling and verification of embedded systems (2002) [1 citations — 0 self]

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by Mauricio Varea, Mauricio Varea
http://www.ecs.soton.ac.uk/~mv99r/publications/theses/MPhil.pdf
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Abstract:

Embedded system design issues become critical as implementation technologies evolve. The interaction between the control and data flow of an embedded system specification is an important consideration and, in order to cope with this aspect, a new internal design representation called Dual Flow Net (DFN) is introduced and further analysed in this thesis. One of the key features of this internal representation is its tight control and data flow interaction, which is achieved by means of two new concepts. Firstly, the structure of the new DFN model is formulated employing a tripartite graph as basis, which turns out to be advantageous for modelling heterogeneous systems. Secondly, a complex domain marking scheme is used to describe the behaviour of the system, leading to better results in terms of modelling the dynamics of the embedded system specification. Structural definitions, behavioural rules and graphical representation of the new DFN model is presented in this work. Besides the potential application of the proposed DFN model in the realm of em-bedded system’s internal design representation, this thesis also addresses the verification of DFN models through formal methods. Behavioural properties of embedded systems,

Citations

2770 Introduction to Automata Theory, Language, and Computation – Hopcroft, Ullman - 1979
1713 Statecharts: A Visual Formalism for Complex Systems – Harel - 1987
1128 Symbolic Model Checking – McMillan - 1992
954 Petri nets: Properties, analysis and applications – Murata - 1989
909 Temporal and modal logic – Emerson - 1990
723 Symbolic Boolean manipulation with ordered binary-decision diagrams – Bryant - 1992
560 Coloured Petri Nets: Basic Concepts, Analysis Methods and – Jensen - 1995
432 Symbolic model checking for real-time systems – Henzinger, Nicollin, et al. - 1994
387 Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems – Buck, Ha, et al. - 1994
353 Computer-Aided Verification of Coordinating Processes – Kurshan - 1994
351 Automata for modeling real-time systems – Alur, Dill - 1990
335 The synchronous data flow programming language – Halbwachs, Caspi, et al. - 1991
259 High-Level Synthesis: Introduction to Chip and System Design – Gajski, Dutt, et al. - 1992
239 Theory of modeling and simulation – Zeigler - 1976
235 Kommunikation mit Automaten – Petri - 1962
222 Automatic symbolic verification of embedded systems – Alur, Ho - 1996
186 Model checking in dense real-time – Alur, Courcoubetis, et al. - 1993
164 Automata-theoretic techniques for modal logics of programs – Vardi, Wolper - 1986
159 The Verilog Hardware Description Language – Thomas, Moorby - 1991
146 Hardware-Software Co-Design of Embedded System – Wolf - 1994
127 Net Theory and the Modelling of Systems – Petri - 1981
121 Using branching time temporal logic to synthesis synchronization skeletons – Emerson, Clarke - 1982
108 The ESTEREL language – Boussinot, Simone - 1991
91 SpecC: specification language and methodology – Gajski, Zhu, et al. - 2000
74 The esterel synchronous programming language and its mathematical semantics – Berry, Cosserat - 1985
72 Hardware/software co-simulation – Rowson - 1994
71 Design of embedded systems: Formal models, validation, and synthesis – Edwards, Lavagno, et al. - 1997
71 VHDL analysis and modeling of digital systems – Navabi - 1997
69 Recoverability of communication protocols – Merlin, Faber - 1976
67 Data Flow Program Graphs – Davis, Keller - 1982
63 Formal Verification in Hardware Design: A Survey – Kern, Greenstreet - 1999
58 Intermediate Microeconomics, A modern approach. Fith edition, W.W – Varian - 1999
55 Automated Transformation of Algorithms into Register-Transfer Level Implementation – Peng, Kuchcinski - 1994
54 High-Level Petri Nets: Theory and Application – Jensen - 1991
53 Using Statecharts for hardware description and synthesis – Drusinsky, Harel - 1989
50 HardwareSoftware co-design of embedded systems: the POLIS approach – Baloron, Giusto, et al. - 1997
46 A hardware implementation of pure Esterel – Berry - 1991
42 Branching vs. linear time: Final showdown – Vardi - 2001
41 Tutorial on highlevel synthesis – McFarland, Parker, et al. - 1988
40 Verification of concurrent programs: The automata-theoretic framework – Vardi - 1991
36 Hardwarec - a language for hardware design (version 2.0 – Ku, Micheli - 1990
34 Challenges for Distributed Event Services: Scalability vs. Expressiveness," presented at – Carzaniga, Rosenblum, et al. - 1999
33 and Branching Structures in the Semantics and Logics of Reactive Systems – Linear - 1985
29 Digital Design: Principles and Practices – Wakerly
25 A Formal Specification Model for Hardware/Software Codesign – Chiodo, Giusto, et al. - 1993
24 Funstate—an internal design representation for codesign – Thiele, Strehl, et al. - 1999
23 Verification of Embedded Systems using a Petri Net based Representation – Cortés, Eles, et al. - 2000
20 Principles of Automated Theorem Proving – Duffy - 1991
20 A unified model for co-simulation and co-synthesis of mixed hardware/software systems – Valderrama - 1995
19 Temporal logics for realtime system specification – Bellini, Mattolini, et al.