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Abstract: In deep sub-micron (DSM) technology, wires are equally or more important than logic components since wire-related problems such as crosstalk, noise are much critical in system-on-chip (SoC) design. Recently, a method [12] for generating a partial product reduction tree (PPRT) with optimal-timing using bit-level adders to implement arithmetic circuits, which outperforms the current best designs, is proposed. However, in the conventional approaches including [12], interconnects are not primary... (Update)
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BibTeX entry: (Update)
@misc{ um-layoutaware,
author = "Junhyung Um and Taewhan Kim",
title = "Layout-Aware Synthesis of Arithmetic Circuits",
url = "citeseer.ist.psu.edu/um02layoutaware.html" }
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