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Abstract: Disjoint Eager Execution (DEE) has demonstrated Instruction Level Parallelism (ILP) speedups of a factor of 30 in simulations[15]. Theoretical and practical arguments verifying these gains are presented. This includes the use of Amdahl's Law, analysis of the partial trace of a detailed simulation of a SPECint92 benchmark, and analysis of the effect on cycle time of the scheduling hardware of the proposed Levo DEE-realization prototype. The static tree heuristic used to economically realize DEE ... (Update)
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...PE is fully pipelined (one result per cycle) 3. 2 Other Logic The detailed equations for the SEN logic and FBD setting logic appear in [10] and [8] respectively. The rest of the detailed equations for the Levo logic will be published at a later date. Prediction Logic: The...
Cited by: More
Overview of the Levo High-ILP Computer - Uht (1997) (Correct)
Active bibliography (related documents): More All
1.2: Verification of ILP Speedups in the 10's for Disjoint Eager.. - Uht (1997) (Correct)
0.2: The Multiscalar Architecture - Franklin (1993) (Correct)
0.2: Partitioning for Complex Objectives - Pinar, Hendrickson (2001) (Correct)
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0.5: High Performance Memory System for High ILP Microarchitectures - Uht (1997) (Correct)
0.5: Levo: IPC in the 10's via Resource Flow Computing - Uht, Morano, Khalafi, de.. (2001) (Correct)
0.4: Data References for: "Reducing the Ill Effects of Branches" - Uht, Sindagi, al. (1996) (Correct)
BibTeX entry: (Update)
A. K. Uht. Verification of ILP Speedups in the 10's for Disjoint Eager Execution. Technical Report 0697-0001, Rev. A, Department of Electrical and Computer Engineering, University of Rhode Island, July 1997. Available via http://www.ele.uri.edu/uht. http://citeseer.ist.psu.edu/uht97verification.html More
@misc{ uht97verification,
author = "A. Uht",
title = "Verification of ILP Speedups in the 10's for Disjoint Eager Execution",
text = "A. K. Uht. Verification of ILP Speedups in the 10's for Disjoint Eager
Execution. Technical Report 0697-0001, Rev. A, Department of Electrical
and Computer Engineering, University of Rhode Island, July 1997. Available
via http://www.ele.uri.edu/uht.",
year = "1997",
url = "citeseer.ist.psu.edu/uht97verification.html" }
Citations (may not include all citations):269 Multiscalar Processors - Sohi, Breach et al. - 1995
230 Limits of Instruction-Level Parallelism - Wall - 1993
160 IMPACT: An Architectural Framework for Multiple-Instruction-.. - Chang, Mahlke et al. - 1991
157 Limits of Control Flow on Parallelism - Lam, Wilson - 1992
145 Exceeding the Data Flow Limit via Value Prediction - Lipasti, Shen - 1996
58 Dynamic Dependency Analysis of Ordinary Programs - Austin, Sohi - 1992
57 The Inhibition of Potential Parallelism by Conditional Jumps (context) - Riseman, Foster - 1972
49 The Performance Potential of Data Dependence Speculation & C.. - Sazeides, Vassiliadis et al. - 1996
47 Disjoint Eager Execution: An Optimal Form of Speculative Exe.. - Uht, Sindagi - 1995
36 Tuning the Pentium Pro Microarchitecture (context) - Papworth - 1996
17 Concurrency Extraction via Hardware Methods Executing the St.. (context) - Uht - 1992
16 Branch Effect Reduction Techniques (context) - Uht, Sindagi et al. - 1997
10 A Theory of Reduced and Minimal Procedural Dependencies (context) - Uht - 1991
9 Hardware Extraction of Low-Level Concurrency from Sequential.. (context) - Uht - 1985
4 Personal communications (context) - Colwell - 1996
2 System for Extracting Low-Level Concurrency from Serial Inst.. (context) - Uht - 1993
Documents on the same site (http://www.ele.uri.edu/~uht/papers/papers.html): More
Data References for: "Branch Effect Reduction Techniques" - Uht, Sindagi, al. (1997) (Correct)
Verification of ILP Speedups in the 10's for Disjoint Eager.. - Uht (1997) (Correct)
Data References for: "Reducing the Ill Effects of Branches" - Uht, Sindagi, al. (1996) (Correct)
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