Augustus K. Uht, David Morano, Alireza Khalafi, Marcos de Alba, Thomas Wenisch, Maryam Ashouei, David Kaeli  Home/Search
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Abstract: High ILP (Instruction Level Parallelism) exists in typical integer codes. Our goal is to create a machine called Levo that will realize this potential ILP in the face of real hardware limitations. Levo is modeled and evaluated at three different levels of abstraction. FastLevo models the potential of Levo via high-level trace-driven simulation embodying key hardware constraints. LevoSim is a detailed cycle-accurate execution-driven simulator; it gives us precise performance data on the... (Update)
Active bibliography (related documents): More All
0.5: Overview of the Levo High-ILP Computer - Uht (1997) (Correct)
0.4: Understanding Eager Evaluation of Imperative Instruction.. - Uht, Wang (1990) (Correct)
0.2: Verification of ILP Speedups in the 10's for Disjoint Eager.. - Uht (1997) (Correct)
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2.4: Levo: IPC in the 10's via Resource Flow Computing - Uht, Morano, Khalafi, de.. (2001) (Correct)
1.1: Realizing High IPC Using Time-Tagged Resource-Flow.. - Uht, Khalafi, Morano.. (2002) (Correct)
0.5: High Performance Memory System for High ILP Microarchitectures - Uht (1997) (Correct)
BibTeX entry: (Update)
@misc{ uht-ipc,
author = "Augustus K. Uht and David Morano and Alireza Khalafi and Marcos de Alba
and Thomas Wenisch and Maryam Ashouei and David Kaeli",
title = "IPC in the 10s via Resource Flow Computing with Levo",
url = "citeseer.ist.psu.edu/uht01ipc.html" }
Citations (may not include all citations):255 Virtual Time (context) - Jefferson - 1985
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157 Limits of Control Flow on Parallelism - Lam, Wilson - 1992
150 An Efficient Algorithm for Exploiting Multiple Arithmetic Un.. (context) - Tomasulo - 1967
75 Measuring Parallelism in Computation-Intensive Scientific/En.. (context) - Kumar - 1988
57 The Inhibition of Potential Parallelism by Conditional Jumps (context) - Riseman, Foster - 1972
49 The Performance Potential of Data Dependence Speculation & C.. - Sazeides, Vassiliadis et al. - 1996
47 Disjoint Eager Execution: An Optimal Form of Speculative Exe.. - Uht, Sindagi - 1995
28 Register Traffic Analysis for Streamlining Inter-Operation C.. - Franklin, Sohi - 1992
19 HPS, a New Microarchitecture: Rationale and Introduction (context) - Patt, Hwu et al. - 1985
17 Circuits for Wide-Window Superscalar Processors - Henry, Kuszmaul et al. - 2000
17 The Architecture of an Optimistic CPU: The Warp Engine - Cleary, Pearson et al. - 1995
16 Branch Effect Reduction Techniques (context) - Uht, Sindagi et al. - 1997
15 Control Speculation in Multithreaded Processors through Dyna.. - Tubella, Gonzalez - 1998
12 Superspeculative Microarchitecture for Beyond AD - Lipasti, Shen
10 A Theory of Reduced and Minimal Procedural Dependencies (context) - Uht - 1991
7 The Ultrascalar Processor: An Asymptotically Scalable Supers.. - Henry, Kuszmaul et al. - 1998
3 An Efficient Hardware Algorithm to Extract Concurrency From .. (context) - Uht - 1986
1 Gate Count Capacity Metrics for FPGAs (context) - Staff
1 HDLevo - VHDL Modeling of Levo Processor Components (context) - Wenisch, Uht
1 Data Flow Systems - Special Issue (context) - Agerwala - 1982
1 Intel 1Q01 Earnings Plummet (context) - Krewell - 2001
Documents on the same site (http://www.ele.uri.edu/~uht/papers/papers.html): More
Data References for: "Branch Effect Reduction Techniques" - Uht, Sindagi, al. (1997) (Correct)
Verification of ILP Speedups in the 10's for Disjoint Eager.. - Uht (1997) (Correct)
Data References for: "Reducing the Ill Effects of Branches" - Uht, Sindagi, al. (1996) (Correct)
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