(Enter summary)
Abstract: As processors continue to exploit more instruction
level parallelism, a greater demand is placed on reducing
the effects of memory access latency. In this paper, we
introduce a novel modification of the processor pipeline
called memory renaming. Memory renaming applies
register access techniques to load instructions, reducing
the effect of delays caused by the need to calculate effective
addresses for the load and all preceding stores
before the data can be fetched. Memory renaming allows
the... (Update)
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BibTeX entry: (Update)
Gary S. Tyson and Todd M. Austin. Improving the accuracy and performance of memory communication through renaming. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 218--227, December 1--3, 1997. http://citeseer.ist.psu.edu/tyson97improving.html More
@inproceedings{ tyson97improving,
author = "Gary S. Tyson and Todd M. Austin",
title = "Improving the Accuracy and Performance of Memory Communication Through Renaming",
booktitle = "International Symposium on Microarchitecture",
pages = "218-227",
year = "1997",
url = "citeseer.ist.psu.edu/tyson97improving.html" }
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