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Improving the Accuracy and Performance of Memory Communication Through Renaming (1997)  (Make Corrections)  (61 citations)
Gary S. Tyson, Todd M. Austin
International Symposium on Microarchitecture



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Abstract: As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the effects of memory access latency. In this paper, we introduce a novel modification of the processor pipeline called memory renaming. Memory renaming applies register access techniques to load instructions, reducing the effect of delays caused by the need to calculate effective addresses for the load and all preceding stores before the data can be fetched. Memory renaming allows the... (Update)

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BibTeX entry:   (Update)

Gary S. Tyson and Todd M. Austin. Improving the accuracy and performance of memory communication through renaming. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 218--227, December 1--3, 1997. http://citeseer.ist.psu.edu/tyson97improving.html   More

@inproceedings{ tyson97improving,
    author = "Gary S. Tyson and Todd M. Austin",
    title = "Improving the Accuracy and Performance of Memory Communication Through Renaming",
    booktitle = "International Symposium on Microarchitecture",
    pages = "218-227",
    year = "1997",
    url = "citeseer.ist.psu.edu/tyson97improving.html" }
Citations (may not include all citations):
222   MIPS RISC Architecture (context) - Kane, Heinrich - 1992
190   Value locality and load value prediction - Lipasti, Wilkerson et al. - 1996
177   Evaluating future microprocessors: The simplescalar tool set - Burger, Austin et al. - 1996
102   Dynamic speculation and synchronization of data dependences - Moshovos, Breach et al. - 1997
93   Optimization of instruction fetch mechanisms for high issue .. - Conte, Menezes et al. - 1995
38   Zero-cycle loads: Microarchitecture support for reducing loa.. - Austin, Sohi - 1995
37   Look-ahead processors (context) - Keller - 1975
14   Two-level adaptive branch prediction (context) - Yeh, Patt - 1991
8   Reducing memory traffic with cregs - Dahl, O'Keefe - 1994
8   Microprocessor Report (context) - pentium, to - 1995
5   The performance potential of data dependence speculation and.. - Sazeidis, Vassiliadis et al. - 1996



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Documents on the same site (http://www.cse.ogi.edu/~taustin/):
On High-Bandwidth Data Cache Design for Multi-Issue Processors - Rivers, al. (1997)   (Correct)

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