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Abstract: As processor performance continues to improve, more emphasis must be placed on the performance of the memory system. In this paper, a detailed characterization of data cache behavior for individual load instructions is given. We show that by selectively applying cache line allocation according the characteristics of individual load instructions, overall performance can be improved for both the data cache and the memory system. This approach can improve some aspects of memory performance by as... (Update)
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BibTeX entry: (Update)
Gary Tyson, Matthew Farrens, John Matthews, and Andrew R. Pleszkun. A modified approach to data cache management. In Proceedings of the 28th Annual ACM/IEEE International Symposium on Microarchitecture, pages 93--103, December 1995. http://citeseer.ist.psu.edu/tyson95modified.html More
@inproceedings{ tysonmodified,
author = "Gary Tyson and Matthew Farrens and John Matthews and Andrew R. Pleszkun",
title = "A Modified Approach to Data Cache Management",
pages = "93--103",
url = "citeseer.ist.psu.edu/tyson95modified.html" }
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110 Improving the Accuracy of Dynamic Branch Prediction Using Br.. (context) - Pan, So et al. - 1992
103 Predicting Conditional Branch Directions from Previous Runs .. (context) - Fisher, Freudenberger - 1992
96 Effective Hardware Based Data Prefetching for High-Performan.. (context) - Chen, Baer - 1995
71 An Area Model for On-Chip Memories and its Application (context) - Mulder, Quach et al. - 1991
70 Two-Level Adaptive Training Branch Prediction - Yeh, Patt - 1991
40 An Analytical Access Time Model for On-Chip Cache Memories (context) - Wada, Rajan et al. - 1992
24 Fast and Accurate Instruction Fetch and Branch Prediction (context) - Calder, Grunwald - 1994
15 Predictability of Load/Store Instruction Latencies (context) - Abraham, Sugumar et al. - 1993
3 Data Cache Performance and Supercomputer Applications (context) - Callahan, Porterfield
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