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Abstract: A simultaneous multithreading (SMT) processor can issue instructions from several threads every cycle, allowing it to effectively hide various instruction latencies; this effect increases with the number of simultaneous contexts supported. However, each added context on an SMT processor incurs a cost in complexity, which may lead to an increase in pipeline length or a decrease in the maximum clock rate. This paper presents new designs for multithreaded processors which combine a conservative... (Update)
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BibTeX entry: (Update)
@misc{ tune-balanced,
author = "Eric Tune and Rakesh Kumar and Dean M. Tullsen and Brad Calder",
title = "Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading
Hierarchy",
url = "citeseer.ist.psu.edu/tune04balanced.html" }
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