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Abstract: The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism available in general-purpose application programs. Unlike other CMAs that rely primarily on hardware for run-time dependence detection and speculation, the... (Update)
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BibTeX entry: (Update)
J.-Y. Tsai, J. Huang, C. Amlo, D. J. Lilja and P.-C. Yew. "The Superthreaded Processor Architecture". In IEEE Transaction on Computers, vol. 48, no. 9, Sep., 1999, Pages ??. http://citeseer.ist.psu.edu/tsai99superthreaded.html More
@article{ tsai99superthreaded,
author = "Jenn-Yuan Tsai and Jian Huang and Christoffer Amlo and David J. Lilja and Pen-Chung Yew",
title = "The Superthreaded Processor Architecture",
journal = "IEEE Transactions on Computers",
volume = "48",
number = "9",
pages = "881-902",
year = "1999",
url = "citeseer.ist.psu.edu/tsai99superthreaded.html" }
Citations (may not include all citations):269 Multiscalar processors - Sohi, Breach et al. - 1995 ACM DBLP
251 Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers et al. - 1995 DBLP
230 Limits of instruction-level parallelism - Wall - 1991 ACM DBLP
193 Superscalar Microprocessor Design (context) - Johnson - 1991
177 Evaluating Future Microprocessors: The Simple Scalar Tool Se.. - Burger, Austin et al.
157 Limits of control flow on parallelism - Lam, Wilson - 1992 ACM DBLP
98 High-Performance Compilers for Parallel Computing (context) - Wolfe - 1996
93 High-bandwidth data memory systems for superscalar processor.. (context) - Sohi, Franklin - 1991 ACM DBLP
70 The expandable split window paradigm for exploiting finegrai.. - Franklin, Sohi - 1992
69 Single instruction stream parallelism is greater than two (context) - Butler, Yeh et al. - 1991 ACM DBLP
67 An Elementary Processor Architecture with Simultaneous Instr.. (context) - Hirata, Kimura et al. - 1992 ACM DBLP
45 Enhanced modulo scheduling for loops with conditional branch.. - Warter, Haab et al. - 1992 ACM DBLP
36 architecture: Compiler-assisted fine-grained multithreading (context) - Dubey, O'Brien et al. - 1995
32 A Variable Instruction Stream Extension to the VLIW Architec.. (context) - Wolfe, Shen - 1991 ACM DBLP
32 Trace Processors: Moving to Fourth Generation Microarchitect.. (context) - Smith, Vajapeyam - 1997
28 Technical Report CSL-TR (context) - Smith, pixie et al. - 1991
13 The superthreaded architecture: Thread pipelining with run-t.. (context) - Tsai, Yew - 1996
8 An Efficient Strategy for Developing a Simulator for a Novel.. - Huang, Lilja - 1998
6 Compiler techniques for concurrent multithreading with hardw.. - Li, Tsai et al. - 1996 ACM DBLP
5 Statement reordering for doacross loops (context) - Chen, Yew - 1994
3 Performance Study of a Concurrent Multithreaded Processor (context) - Tsai, Jiang et al. - 1998 ACM DBLP
2 Program optimization for concurrent multithreaded architectu.. (context) - Tsai, Jiang et al. - 1997
1 Yevgeny Gurevich and Whay S (context) - Fillo, Keckler et al. - 1995
The graph only includes citing articles where the year of publication is known.
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