SUPPORT FOR FAULT TOLERANCE IN VLSI PROCESSORS †
Abstract:
Fault tolerance techniques are used to allow computer systems to continue correct operation despite component failure. Hardware-supported concurrent error-detection and limited fault tolerance in system components, as implemented by coding or replication, are often required. Detection latency can be reduced by increasing the visibility of internal module state using compressed ‘‘signatures’ ’ of internal values. Thus, encoders, decoders, comparators, and data compression circuitry are of critical importance in fault-tolerant VLSI systems. In this paper we describe alternative implementations of such circuits and various ways in which they can be connected in VLSI modules. We also describe possible performance enhancements through the use of a technique, called micro rollback, which allows error detection to be performed in parallel with inter-module communication. As a concrete example, we present area and performance measurements of alternative microarchitectures and circuits that can be used to add detection and correction to a VLSI RISC processor we are implementing. I.
Citations
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