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Abstract: In order to achieve fault tolerance, highly reliable systems often require hardware-supported concurrent error detection for all system components. Checkers are connected in the communication paths from each module to the rest of the system, reducing system performance by requiring either longer clock cycles or additional pipeline stages. The performance penalty of concurrent error detection can be minimized by performing the checks in parallel with the transmission of information between... (Update)
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BibTeX entry: (Update)
@misc{ tremblay-faulttolerance,
author = "Marc Tremblay and Yuval Tamir",
title = "Fault-Tolerance for High-Performance Multi-Module VLSI Systems Using Micro
Rollback",
url = "citeseer.ist.psu.edu/tremblay89faulttolerance.html" }
Citations (may not include all citations):352 Time, Clocks, and the Ordering of Events in a Distributed Sy.. (context) - Lamport - 1978
52 Reliability Issues in Computing System Design (context) - Randell, Lee et al. - 1978
30 Checkpoint Repair for Out-of-order Execution Machines (context) - Hwu, Patt - 1987
28 Reduced Instruction Set Computer Architectures for VLSI (context) - Katevenis - 1983
14 Fault Detection Capabilities of Alternating Logic (context) - Reynolds, Metze - 1976
5 Fault Handling on the IBM 4341 Processor (context) - Ciacelli - 1981
4 Logic Design of Fault-Tolerant Arithmetic Units Based on the.. (context) - Takeda, Tohma - 1980
3 The Implementation and Application of Micro Rollback in Faul.. - Tamir, Tremblay et al. - 1988
2 Am29000 Streamlined Instruction Processor User's Manual (context) - Devices - 1987
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